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Lim, Sung Kyu

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Author: Minz, Jacob Rajkumar × search.filters.applied.f.isOrgUnitOfPublicationTitle: Center for Experimental Research in Computer Systems ×

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Channel and Pin Assignment for Three Dimensional Packaging Routing

2004-05-24 , Minz, Jacob Rajkumar , Lim, Sung Kyu

Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. The contribution of this work is threefold: (i) formulation of the new 3-dimensional global routing problem, (ii) a new routing flow that considers the various design constraints unique to SOP, and (iii) a global router for the technology. Our related experimental results demonstrate the effectiveness of our algorithm.

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Global Routing Paradigm for System-on-Package

2003 , Minz, Jacob Rajkumar , Pathak, Mohit , Lim, Sung Kyu

The true potential of three dimensional System-On-Package (SOP) technology lies in its capability to integrate both active and passive components into a single high speed/density multi-layer packaging substrate. We propose a new interconnect-centric SOP global routing algorithm that handles arbitrary routing topologies and produces near optimal results. The contribution of this work is threefold: (i) modeling of the SOP routing resource, (ii) formulation of the new SOP global routing problem, and (iii) development of a fast and novel algorithm that considers the various design constraints unique to SOP. Our related experimental results demonstrate the effectiveness of our algorithm

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Congestion and Power Integrity Aware Placement and Routing for 3D Packaging

2004-04-23 , Minz, Jacob Rajkumar , Choi, Jinwoo , Swaminathan, Madhavan , Lim, Sung Kyu

One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion trade-off. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.

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Global Routing for Three Dimensional Packaging

2003 , Minz, Jacob Rajkumar , Lim, Sung Kyu

Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. The contribution of this work is threefold: (i) formulation of the new 3-dimensional global routing problem, (ii) a new routing flow that considers the various design constraints unique to SOP, and (iii) a global router for the technology. Our related experimental results demonstrate the effectiveness of our algorithm.

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Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design

2003 , Ekpanyapong, Mongkol , Minz, Jacob Rajkumar , Watewai, Thaisiri , Lee, Hsien-Hsin Sean , Lim, Sung Kyu

As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying the performance scalability substantially. An effective floorplanning algorithm can no longer ignore the information of dynamic communication patterns of applications. In this paper, using the profile information acquired at the architecture/microarchitecture level, we propose a "profile-guided microarchitectural floorplanner" that considers both the impact of wire delay and the architectural behavior, namely the inter-module communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on our simulation results, the profile-guided method shows a 5% to 40% IPC improvement when clock frequency is fixed. From the perspective of instruction throughput (in BIPS), our floorplanner is much more scalable than a conventional wire length based floorplanner.

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Layer Assignment for System on Packages

2003 , Minz, Jacob Rajkumar , Lim, Sung Kyu

The routing environment for the new emerging mixed-signal System-on-Package (SOP) technology is more advanced than that of the conventional PCB or MCM technology - pins are located at all layers of SOP packaging substrate rather than the top-most layer only. We propose a new interconnect-centric layer assignment algorithm named LA-SOP that handles arbitrary routing topologies and produces near optimal results. The contribution of this work is threefold: (i) modeling of the SOP routing resource, (ii) formulation of the new SOP layer assignment problem, and (iii) development of a fast and novel algorithm that considers the various design constraints unique to SOP. We review various approaches for the PCB, IC and MCM algorithms and investigate their applicability to the SOP model. Our related experimental results demonstrate the effectiveness of our algorithm LA-SOP.

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