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School of Electrical and Computer Engineering

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College of Engineering

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https://finding-aids.library.gatech.edu/agents/corporate_entities/154

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Now showing 1 - 10 of 4410

Throughput optimization in MIMO networks

(Georgia Institute of Technology, 2011-08-22) Srinivasan, Ramya ; Blough, Douglas M. ; Ammar, Mostafa ; Ferri, Bonnie ; Ingram, Mary Ann ; Sivakumar, Raghupathy ; Electrical and Computer Engineering

Enabling multi-hop wireless mesh networks with multi-input multi-output (MIMO) functionality boosts network throughput by transmitting over multiple orthogonal spatial channels (spatial multiplexing) and by performing interference cancellation, to allow links within interference range to be concurrently active. Furthermore, if the channel is in a deep fade, then multiple antenna elements at the transmitter and/or receiver can be used to transmit a single stream, thereby improving signal quality (diversity gain). However, there is a fundamental trade-off between boosting individual link performance and reducing interference, which must be modeled in the process of optimizing network throughput. This is called the diversity-multiplexing-interference suppression trade-off. Optimizing network throughput therefore, requires optimizing the trade-off between the amounts of diversity employed on each link, the number of streams multiplexed on each link and the number of interfering links allowed to be simultaneously active in the network. We present a set of efficient heuristics for one-shot link scheduling and stream allocation that approximately solve the problem of optimizing network throughput in a single time slot. We identify the fundamental problem of verifying the feasibility of a given stream allocation. The problems of general link scheduling and stream allocation are very closely related to the problem of verifying feasibility. We present a set of efficient heuristic feasibility tests which can be easily incorporated into practical scheduling schemes. We show for some special MIMO network scenarios that feasibility is of polynomial complexity. However, we conjecture that in general, this problem, which is a variation of Boolean Satisablility, is NP-Complete.
HoneyPhy: A physics-aware CPS honeypot framework

(Georgia Institute of Technology, 2017-04-28) Litchfield, Samuel Lewis ; Beyah, Raheem A. ; Meliopoulos, Sakis A. P. ; Owen, Henry L. ; Electrical and Computer Engineering

Cyber Physical Systems (CPS) are vulnerable systems, and attacks are currently being carried out against them. Some of these attacks have never been seen before, and so the first step in defending CPS is to understand what attackers are doing, and how they are doing it. Traditionally, honeypots have been a tool used to gain this information, but honeypots need to be convincing to fool attackers. For CPS, being convincing entails not only ad- dressing networking concerns, but also modeling device actuation fingerprints and how the attached process responds to actuations. In order to create a convincing CPS honeypot, a framework was developed to address the need to present convincing networking, device, and process fingerprints. Two proof of concept systems were developed for this framework, and a set of proof of concept device and process models were implemented.
Ultrasonic phased arrays with variable geometric focusing for hyperthermia applications

(Georgia Institute of Technology, 1991-12) Yoon, Young Joong ; Benkeser, Paul J. ; Electrical Engineering
A Bayesian least squares support vector machines based framework for fault diagnosis and failure prognosis

(Georgia Institute of Technology, 2010-07-21) Khawaja, Taimoor Saleem ; Vachtsevanos, George J. ; Jennifer Michaels ; Linda Wills ; Saad, Ashraf ; Wardi, Yorai ; Electrical and Computer Engineering

A high-belief low-overhead Prognostics and Health Management (PHM) system is desired for online real-time monitoring of complex non-linear systems operating in a complex (possibly non-Gaussian) noise environment. This thesis presents a Bayesian Least Squares Support Vector Machine (LS-SVM) based framework for fault diagnosis and failure prognosis in nonlinear, non-Gaussian systems. The methodology assumes the availability of real-time process measurements, definition of a set of fault indicators, and the existence of empirical knowledge (or historical data) to characterize both nominal and abnormal operating conditions. An efficient yet powerful Least Squares Support Vector Machine (LS-SVM) algorithm, set within a Bayesian Inference framework, not only allows for the development of real-time algorithms for diagnosis and prognosis but also provides a solid theoretical framework to address key concepts related to classication for diagnosis and regression modeling for prognosis. SVM machines are founded on the principle of Structural Risk Minimization (SRM) which tends to nd a good trade-o between low empirical risk and small capacity. The key features in SVM are the use of non-linear kernels, the absence of local minima, the sparseness of the solution and the capacity control obtained by optimizing the margin. The Bayesian Inference framework linked with LS-SVMs allows a probabilistic interpretation of the results for diagnosis and prognosis. Additional levels of inference provide the much coveted features of adaptability and tunability of the modeling parameters. The two main modules considered in this research are fault diagnosis and failure prognosis. With the goal of designing an efficient and reliable fault diagnosis scheme, a novel Anomaly Detector is suggested based on the LS-SVM machines. The proposed scheme uses only baseline data to construct a 1-class LS-SVM machine which, when presented with online data, is able to distinguish between normal behavior and any abnormal or novel data during real-time operation. The results of the scheme are interpreted as a posterior probability of health (1 - probability of fault). As shown through two case studies in Chapter 3, the scheme is well suited for diagnosing imminent faults in dynamical non-linear systems. Finally, the failure prognosis scheme is based on an incremental weighted Bayesian LS-SVR machine. It is particularly suited for online deployment given the incremental nature of the algorithm and the quick optimization problem solved in the LS-SVR algorithm. By way of kernelization and a Gaussian Mixture Modeling (GMM) scheme, the algorithm can estimate (possibly) non-Gaussian posterior distributions for complex non-linear systems. An efficient regression scheme associated with the more rigorous core algorithm allows for long-term predictions, fault growth estimation with confidence bounds and remaining useful life (RUL) estimation after a fault is detected. The leading contributions of this thesis are (a) the development of a novel Bayesian Anomaly Detector for efficient and reliable Fault Detection and Identification (FDI) based on Least Squares Support Vector Machines , (b) the development of a data-driven real-time architecture for long-term Failure Prognosis using Least Squares Support Vector Machines,(c) Uncertainty representation and management using Bayesian Inference for posterior distribution estimation and hyper-parameter tuning, and finally (d) the statistical characterization of the performance of diagnosis and prognosis algorithms in order to relate the efficiency and reliability of the proposed schemes.
Scalable RTI-Based Parallel Simulation of Networks

(Georgia Institute of Technology, 2003-06) Perumalla, Kalyan S. ; Park, Alfred ; Fujimoto, Richard M. ; Riley, George F. ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. School of Electrical and Computer Engineering

Federated simulation interfaces such as the High Level Architecture (HLA) were designed for interoperability, and as such are not traditionally associated with high performance computing. In this paper, we present results of a case study examining the use of federated simulations using runtime infrastructure (RTI) software to realize large-scale parallel network simulators. We examine the performance of two different federated network simulators, and describe RTI performance optimizations that were used to achieve efficient execution. We show that RTI-based parallel simulations can scale extremely well and achieve very high speedup. Our experiments yielded more than 80-fold scaled speedup in simulating large TCP/IP networks, demonstrating performance of up to 6 million simulated packet transmissions per second on a Linux cluster. Networks containing up to two million network nodes (routers and end systems) were simulated.
Development of high-efficiency boron diffused silicon solar cells

(Georgia Institute of Technology, 2012-05-04) Das, Arnab ; Rohatgi, Ajeet ; Bernard Kippelen ; Citrin, David ; Riley, George F. ; Phillip First ; Electrical and Computer Engineering

The objective of the proposed research is to develop low-cost, screen-printed 20% efficient silicon solar cells. In the first part of this thesis, a ~19% efficient, screen-printed cell was fabricated using the commercially-dominant aluminum back surface field (Al-BSF) cell structure. Device modeling was then used to determine that increasing the efficiency to 20% required improvements in both back surface passivation and rear reflectance. In the second part of this thesis, a passivated, transparent boron BSF (B-BSF) structure was proposed as a high-throughput method for realizing these improvements. The first step in fabricating the proposed B-BSF cell involved the successful development of a water-based, spin-on solution of boric acid as a low-cost, non-toxic and non-pyrophoric alternative to common boron diffusion sources such as boron tribromide. A review of the literature shows that a common problem with boron diffusion is severe bulk lifetime degradation, with Fe contamination being commonly speculated as the cause. An experimental study was therefore devised in which the impact of boron diffusion and subsequent cell process steps on the bulk lifetime and bulk iron contamination was tracked. From this study, a model for boron diffusion-induced Fe contamination was developed along with methods for gettering Fe from the substrate. A key achievement of this thesis was the discovery of a novel, negatively charged, aluminum-doped spin-on glass (SOG) which can, in a short thermal step, simultaneously getter Fe and provide stable, high-quality passivation of planar, boron-diffused Si surfaces. Since past attempts at achieving low-cost, high-efficiency, boron-diffused cells have suffered from bulk lifetime degradation and difficulties with passivating a boron-diffused Si surface, the Al-doped SOG provides a solution to both challenges. Since a high rear reflectance is important for achieving high-efficiencies, an experimental study of various reflectors was undertaken and a silver colloid material was found which exhibits both high electrical conductivity and Lambertian reflectance >95%. The work on boric acid diffusion, iron gettering, surface passivation and rear reflectors was successfully integrated into a 20.2% efficient, screen-printed, B-BSF cell fabricated on 300 µm thick, p-type float-zone (FZ) Si wafers. Both device theory and modeling was used to show that, due to its well-passivated surfaces, this cell would suffer a large loss in efficiency due to light-induced degradation (LID) if it were fabricated on commercial p-type Czochralski (Cz) Si substrates. Since n-type Si substrates do not suffer from LID, the p-type process was slightly tweaked and applied to n-type FZ wafers, resulting in 20.3% efficient cells on 190 µm thick wafers. Computer modeling shows that both the p-type and n-type cells can maintain efficiencies of 20% for wafers as thin as 100 µm.
Product quality modeling and control based on vision inspection with an application to baking processes

(Georgia Institute of Technology, 2005-04-14) Zhang, Yingchuan ; Michaels, Jennifer E. ; Bonnie Heck Ferri ; Farrokh, Ayazi ; Vachtsevanos, George J. ; Egerstedt, Magnus ; Sheldon M. Jeter ; Electrical and Computer Engineering

Manufacturing industries are facing major challenges in terms of improving product quality and increasing throughput while sustaining production costs to acceptable levels. Product-oriented processes, both legacy and new, are poorly monitored and controlled on the basis of distributed loop controllers that are aiming to maintain critical process variables within acceptable bounds. Thus, poor quality product results when such processes are subjected to large disturbances - operational failures, environmental changes, and changes in loading conditions. In this research, product quality modeling and control based on a vision inspection methodology is proposed to improve product quality and increase productivity. The main contributions of this research are twofold. First, this research introduces a product quality modeling methodology that combines both physical-based modeling and data-driven modeling. The quality model is the link between information coming from the inspection of product features and the specification of process control strategies. It is essential to control and optimize the process. Physical-based modeling is used to model the product temperature profile, and data-driven modeling is used to train the mapping from the product temperature profile to each quality metric. The break down of the sub models increase the flexibility of model development and reduce the effort to change the model when the quality metrics change. The second contribution is the development of a novel approach to control product quality based on vision inspection, which is developed as part of a hybrid, hierarchical architecture. The high-level control module involves scheduling of multiple plant processes, diagnostics of the failure condition in the process, and the supervision of the whole process. The mid-level control module, which is the focus of the work presented here, takes advantage of baking product quality indicators and oven parameter measurements to optimize zone temperature and conveyor speed set points so that the best product quality is achieved even in the presence of disturbances. The low-level control module consists of basic control loops. Each of them controls parameters of each operation in the process separately. They are generally simple and easy to implement.
Intersubband dynamics in semiconductor quantum wells

(Georgia Institute of Technology, 2007-07-01) Citrin, David S. ; Georgia Institute of Technology. Office of Sponsored Programs ; Georgia Institute of Technology. School of Electrical and Computer Engineering
Interference analysis and mitigation for heterogeneous cellular networks

(Georgia Institute of Technology, 2014-08-19) Gutierrez Estevez, David Manuel ; Akyildiz, Ian F. ; Bloch, Matthieu ; Xu, Jun ; Li, Geoffrey Y. ; Barry, John R. ; Electrical and Computer Engineering

The architecture of cellular networks has been undergoing an extraordinarily fast evolution in the last years to keep up with the ever increasing user demands for wireless data and services. Motivated by a search for a breakthrough in network capacity, the paradigm of heterogeneous networks (HetNets) has become prominent in modern cellular systems, where carefully deployed macrocells coexist with layers of irregularly deployed cells of reduced coverage sizes. Users can thus be offloaded from the macrocell and the capacity of the network increases. However, universal frequency reuse is usually employed to maximize capacity gains, thereby introducing the fundamental problem of inter-cell interference (ICI) in the network caused by the sharing of the spectrum among the different tiers of the HetNet. The objective of this PhD thesis is to provide analysis and mitigation techniques for the fundamental problem of interference in heterogeneous cellular networks. First, the interference of a two-tier network is modeled and analyzed by making use of spatial statistics tools that allow the reconstruction of complete coverage maps. A correlation analysis is then performed by deriving a spatial coverage cross-tier correlation function. Second, a novel architecture design is proposed to minimize interference in HetNets whose base stations may be equipped with very large antenna arrays, another key technology of future wireless systems. Then, we present interference mitigation techniques for different types of small cells, namely picocells and femtocells. In the third contribution of this thesis, we analyze the case of clustered deployments by proposing and comparing techniques suitable for this scenario. Fourth, we tackle the case of femtocell deployments by analyzing the degrading effect of interference and proposing new mitigation methods. Fifth, we introduce femtorelays, a novel small cell access technology that combats interference in femtocell networks and provides higher backhaul capacity.
Design and Demonstration of 3D Glass Panel Embedded (GPE) Package for Superior Bandwidth and Power-Efficiency

(Georgia Institute of Technology, 2021-05-01) Ravichandran, Siddharth ; Tummala, Rao R. ; Swaminathan, Madhavan ; Peterson, Andrew ; Naeemi, Azad ; Smet, Vanessa ; Electrical and Computer Engineering

With the slowing down of Moore's law, HPC/AI systems today disaggregate large and expensive System-on-Chips (SoCs) and pursue on-package heterogeneous integration to meet the growing demands in compute performance and memory capacity. Hence, the bandwidth and power-efficiency (measured as energy-per-bit) of communication between these smaller chips become the limiting factor in scaling system performance. These two key metrics are primarily driven by I/O count, interconnect length, interconnect density, and the choice of dielectric materials. Today, the technology options for package-level integration are either 2D/3D and chip-first/chip-last, based on how the chips are assembled. While some 3D and chip-first technologies solve the interconnect length and I/O count challenges, they are still fundamentally limited in scaling the bandwidth and power-efficiency comprehensively. This work presents a novel, non-TSV, 3D packaging technology using Glass Panel Embedding (GPE) for next-generation HPC and AI systems with over 1 Tbps/mm bandwidth consuming less than 0.1 pJ/bit power-efficiency. GPE simultaneously addresses I/O density and interconnect length while utilizing low-dk/df materials and low-loss polymer RDL technologies. The design of such a system is presented in this work along with a design-space exploration of key substrate parameters to assess the bandwidth and energy-per-bit potential of proposed structure. Materials and processes are also studied establishing a stable fabrication process flow to demonstrate such a 3D package in a panel-scalable, low-cost, and thermo-mechanically reliable fashion.