Person:

Lim, Sung Kyu

Permanent Link

https://hdl.handle.net/1853/71463

Associated Organization(s)

Organizational Unit

School of Electrical and Computer Engineering

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Publication Search Results

Now showing 1 - 10 of 19

ILP-based Supply and Threshold Voltage Assignment For Total Power Minimization

(Georgia Institute of Technology, 2007) Ekpanyapong, Mongkol ; Korkmaz, Pinar ; Lim, Sung Kyu

In this paper we present an ILP-based method to simultaneously assign supply and threshold voltages to individual gates for dynamic and leakage power minimization. In our three-step approach, low power min-flipflop (FF) retiming is first performed to reduce the clock period while taking the FF delay/power into consideration. Next, the subsequent voltage assignment formulated in ILP makes the best possible supply/threshold voltage assignment under the given clock period constraint set by the retiming. Finally, a post-process further refines the voltage assignment solution by exploiting the remaining timing slack in the circuit. Related experiments show that the min-FF retiming plus simultaneous Vdd/Vth assignment approach outperforms the existing max-FF retiming plus Vdd-only assignment approach.
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors

(Georgia Institute of Technology, 2006) Mohamood, Fayez ; Healy, Michael ; Lim, Sung Kyu ; Lee, Hsien-Hsin Sean

Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, power-hungrier designs. To battle the ever-aggravating power consumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to operate the processor within a given power envelope. However, these techniques often lead to high-frequency current variations, which can stress the power delivery system and jeopardize reliability due to inductive noise (L di/dt) in the power supply network. In addition, with the advent of 3D stacked IC technology that facilitates the design of processors with much higher module density, the design of a low impedance power-delivery network can be a daunting challenge. To counteract these issues, modern microprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capacitance. With the lowering of supply voltages and increased leakage power and current consumption, designing a processor for the worst case is becoming less appealing. In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that will limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt controller is the first that takes the processor's floorplan as well as its power-pin distribution into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D and 3D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0% (2D floorplan) and 3.8% (3D floorplan).
Wire Congestion And Thermal Aware Global Placement For 3D VLSI Circuits

(Georgia Institute of Technology, 2004-05-26) Balakrishnan, Karthik ; Nanda, Vidit ; Easwar, Siddharth Sangam ; Lim, Sung Kyu

The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce global the temperature gradient and local and global congestions of 3D circuit designs without compromising total intra-layer wirelength or inter-layer via count. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local wire congestion and power dissipation. Then, we perform simulated annealing with a full-length thermal analysis to reduce the circuit's global congestion and thermal gradient. Experimental results show that when compared to the standard mincut approach, our thermal gradient and local congestion are reduced by 25% each, global congestion is reduced by over 7%. Moreover, we only see a 10% increase in the wiring length and the number of vias required.
Channel and Pin Assignment for Three Dimensional Packaging Routing

(Georgia Institute of Technology, 2004-05-24) Minz, Jacob Rajkumar ; Lim, Sung Kyu

Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. The contribution of this work is threefold: (i) formulation of the new 3-dimensional global routing problem, (ii) a new routing flow that considers the various design constraints unique to SOP, and (iii) a global router for the technology. Our related experimental results demonstrate the effectiveness of our algorithm.
Congestion and Power Integrity Aware Placement and Routing for 3D Packaging

(Georgia Institute of Technology, 2004-04-23) Minz, Jacob Rajkumar ; Choi, Jinwoo ; Swaminathan, Madhavan ; Lim, Sung Kyu

One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion trade-off. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.
Thermal-aware 3D Microarchitectural Floorplanning

(Georgia Institute of Technology, 2004) Ekpanyapong, Mongkol ; Healy, Michael ; Ballapuram, Chinnakrishnan S. ; Lim, Sung Kyu ; Lee, Hsien-Hsin Sean ; Loh, Gabriel H.

Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper pipelines and higher clock frequency. The move to 3D ICs will also likely be used to further shorten wirelength. This will cause thermal issues to become a major bottleneck to performance improvement. In this paper we propose a floorplanning algorithm which takes into consideration both thermal issues and profile weighted wirelength using mathematical programming. Our profile-driven objective improves performance by 20% over wirelength-driven. While the thermal-driven objective improves temperature by 24% on average over the profile-driven case.
Thermal-driven Circuit Partitioning and Floorplanning with Power Optimization

(Georgia Institute of Technology, 2003) Lee, Kyoung-Keun ; Paradise, Edward J. ; Lim, Sung Kyu

In this paper, we present methodology to distribute the temperature of gates evenly on a chip while simultaneously reducing the power consumption by using newly designed partitioning and floorplanning algorithms. This new partitioning algorithm is designed to partition blocks with well-balanced temperatures by altering the FM algorithm to include thermal constraints. Then, the suggested floorplanning algorithm can assign specific geometric locations to the blocks to refine the quality of the thermal distribution and to reduce power consumption. The combination of these two new algorithms, called TPO, is compared with the results of a conventional design procedure. As a result, power is reduced by up to 19% on average and a well-distributed thermal condition is achieved.
Multi-layer Floorplanning for Reliable System-on-Package

(Georgia Institute of Technology, 2003) Shiu, Pun Hang ; Lim, Sung Kyu

Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner--it must place both active components such as digital IC, analog ICs, memory modules, MEMS, and opto-electronic modules, and embedded passive components such as capacitors, resistors, and inductors in a multi-layer packaging substrate while considering various signal integrity issues. We propose a new interconnect-centric multi-layer floorplanner named MF-SOP, which is based on a multiple objective stochastic Simulated Annealing method. The contribution of this work is first to formulate this new kind of floorplanning problem and then to develop an effective algorithm that handles various design constraints unique to SOP. The related experiments show that the area reduction of MFSOP compared to its 2-D counterpart is on the order of O(k) and wirelength reduction is 48% average for k-layer SOP, while satisfying design constraints.
Simultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming

(Georgia Institute of Technology, 2003) Ekpanyapong, Mongkol ; Lim, Sung Kyu

Delay minimization and power minimization are two important objectives in the design of the high-performance, portable, and wireless computing and communication systems. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a unified framework for multi-level partitioning and floorplanning with retiming, targeting simultaneous delay and power optimization. We first discuss the importance of retiming delay and visible power as opposed to the conventional static delay and total power for sequential circuits. Then we propose GEO-PD algorithm for simultaneous delay and power optimization and provide smooth cutsize, wirelength, power and delay tradeoff. In GEO-PD, we use retiming based timing analysis and visible power analysis to identify timing and power critical nets and assign proper weights to them to guide the multi-level optimization process. In general, timing and power analysis are done at the original netlist while a recursive multi-level approach performs partitioning and floorplanning on the sub-netlist as well as its coarsened representations. We show an effective way to translate the timing and power analysis results from the original netlist to a coarsened sub-netlist for effective multi-level delay and power optimization. To the best of our knowledge, this is the first paper addressing simultaneous delay and power optimization in multi-level partitioning and floorplanning.
Impact of Multi-level Clustering on Performance Driven Global Placement

(Georgia Institute of Technology, 2003) Balakrishnan, Karthik ; Nanda, Vidit ; Ekpanyapong, Mongkol ; Lim, Sung Kyu

Delay and wirelength minimization continue to be important objectives in the design of high-performance computing systems. For large-scale circuits, the clustering process becomes essential for reducing the problem size. However, to the best of our knowledge, there is no study about the impact of multi-level clustering on performance-driven global placement. In this paper, five clustering algorithms including the quasi-optimal retiming delay driven PRIME and the cutsize-driven ESC have been considered for their impact on state-of-the-art mincut based global placement. Results show that minimizing cutsize or wirelength during clustering typically results in significant performance improvements.