Person:
Swaminathan, Madhavan

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End date: 2009 × Start date: 2000 × Item Type: Publication ×

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Modeling and co-simulation of power distribution networked in digitaland mix

2006-01-31 , Swaminathan, Madhavan

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Congestion and Power Integrity Aware Placement and Routing for 3D Packaging

2004-04-23 , Minz, Jacob Rajkumar , Choi, Jinwoo , Swaminathan, Madhavan , Lim, Sung Kyu

One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion trade-off. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.

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Modeling of power supply noise in FPGA

2004-09-01 , Swaminathan, Madhavan

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The design of the power delivery system for next generation gigahertz packages

2003-01-31 , Swaminathan, Madhavan

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Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package

2004-05 , Wong, C. P. , Kang, E. T. , Tay, Andrew A. O. , Wong, E. H. , Swaminathan, Madhavan , Iyer, Mahadevan K. , Rotaru, Mihai D. , Tummala, Rao R. , Doraiswami, Ravi , Ang, Simon S. , Kripesh, V.

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-μm pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.

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Chip-Package Co-Design Methodology for Integrated RF Microsystems

2001-09-15 , Swaminathan, Madhavan

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