Swaminathan, Madhavan

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Now showing 1 - 9 of 9
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    System Scaling Through Heterogeneous Integration
    (Georgia Institute of Technology, 2019-08-27) Swaminathan, Madhavan
    A combination of "Moore" (IC) and "More than Moore" (package) scaling has led to the shrinking of electronic systems over the last several decades. As scaling continues beyond CMOS to include advanced devices, scaling of the package needs to continue to enable system scaling, leading to the integration and miniaturization of systems. This requires new technologies for package integration which when connected to assembled ICs leads to System on Package (SoP) solutions that have superior performance and size as compared to current technologies. This presentation will discuss advanced SoP platforms for integration with a focus on heterogeneity for a variety of applications that include AI, HPC, Power Electronics, mmWave to name a few. The inter-disciplinary nature of the research will be highlighted based on faculty interactions between four different schools at GT.
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    Development of compliant free-standing structures for sub 32-nm multi-core ICs
    (Georgia Institute of Technology, 2012-11) Sitaraman, Suresh K. ; Swaminathan, Madhavan
    With the introduction of on-chip low-K dielectric materials, it is increasingly important to reduce on-chip stresses so that the low-K dielectric material will not crack or delaminate. One way to reduce the thermo-mechanical stresses is to introduce compliant structures between the die and the substrate and thus to decouple the die from the substrate. Decoupling the die from the substrate or the substrate from the board by means of mechanically compliant interconnects will reduce stresses created by the coefficient of thermal expansion mismatch. A decoupled diesubstrate or substrate-board interface will allow the different components to expand or contract differently without inducing high stresses in the components. In this work, we report the design, fabrication, modeling, and characterization of innovative multi-path fan-shaped off-chip compliant interconnects. The proposed interconnects can be fabricated at the wafer-level and are cost-effective, can be of fine pitch and scalable, and will have redundant electrical paths.
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    Modeling and co-simulation of power distribution networked in digitaland mix
    (Georgia Institute of Technology, 2006-01-31) Swaminathan, Madhavan
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    Modeling of power supply noise in FPGA
    (Georgia Institute of Technology, 2004-09-01) Swaminathan, Madhavan
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    Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package
    (Georgia Institute of Technology, 2004-05) Wong, C. P. ; Kang, E. T. ; Tay, Andrew A. O. ; Wong, E. H. ; Swaminathan, Madhavan ; Iyer, Mahadevan K. ; Rotaru, Mihai D. ; Tummala, Rao R. ; Doraiswami, Ravi ; Ang, Simon S. ; Kripesh, V.
    According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-μm pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.
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    Congestion and Power Integrity Aware Placement and Routing for 3D Packaging
    (Georgia Institute of Technology, 2004-04-23) Minz, Jacob Rajkumar ; Choi, Jinwoo ; Swaminathan, Madhavan ; Lim, Sung Kyu
    One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion trade-off. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.
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    The design of the power delivery system for next generation gigahertz packages
    (Georgia Institute of Technology, 2003-01-31) Swaminathan, Madhavan
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    Chip-Package Co-Design Methodology for Integrated RF Microsystems
    (Georgia Institute of Technology, 2001-09-15) Swaminathan, Madhavan
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    Embedded design of rf components in low temperature cofired ceramic (LTCC)
    (Georgia Institute of Technology, 1998) Swaminathan, Madhavan