Title:
Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package
Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package
Author(s)
Wong, C. P.
Kang, E. T.
Tay, Andrew A. O.
Wong, E. H.
Swaminathan, Madhavan
Iyer, Mahadevan K.
Rotaru, Mihai D.
Tummala, Rao R.
Doraiswami, Ravi
Ang, Simon S.
Kripesh, V.
Kang, E. T.
Tay, Andrew A. O.
Wong, E. H.
Swaminathan, Madhavan
Iyer, Mahadevan K.
Rotaru, Mihai D.
Tummala, Rao R.
Doraiswami, Ravi
Ang, Simon S.
Kripesh, V.
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Abstract
According to the latest ITRS roadmap, the pitch of
area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections
needs to be improved to support data rates in excess of 10 Gbps,
while guaranteeing thermomechanical reliability and lowering the
cost. These requirements are challenging, thus, needing innovative
interconnection designs and technologies. This paper describes
the development of three interconnection schemes for wafer-level
packages (WLPs) at 100-μm pitch, involving rigid, compliant, and
semicompliant interconnection technologies, extending the state
of the art in each. Extensive electrical and mechanical modeling
was carried out to optimize the geometry of the interconnections
with respect to electrical performance and thermomechanical
reliability. It was found that the requirements of electrical performance
often conflict with those of thermomechanical reliability
and the final “optimum” design is a tradeoff between the two.
For the three interconnection schemes proposed, it was found that
the electrical requirements can be met fairly well but acceptable
mechanical reliability may require organic boards with coefficient
of thermal expansion of 10 ppm/K or lower.
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Date Issued
2004-05
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Article