Person:
Mooney,
Vincent John, III
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Publication Search Results
Timing Analysis for Preemptive Multi-tasking Real-Time Systems with Caches
Some Layouts Using the Sleepy Stack Approach
Atalanta: A New Multiprocessor RTOS Kernel for System-on-a-Chip Applications
Instruction-level Reverse Execution for Debugging
Loss-Tolerant and Secure Embedded Computing via Inscrutable Instruction-Set Architectures (I²SA)
An O(NIN(M,N)) Parallel Deadlock Detection Algorithm
Round-robin Arbiter Design and Generation
Cache-Related Timing Analysis for Multi-tasking Real-Time Systems with Nested Preemptions
Golay and Wavelet Error Control Codes in VLSI
Automated Bus Generation for Multiprocessor SoC Design