Person:
Mooney, Vincent John, III

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    Lattice-Based Encryption Schemes and its Applications to Homomorphic Encryption
    (Georgia Institute of Technology, 2020-12) Bin Ahmad Shahrir, Ahmad Faris Durrani ; Pan, Leyan ; Hutto, Kevin ; Mooney, Vincent John, III ; College of Computing
    Homomorphic encryption is a type of encryption that allows performing operations on the ciphertext without having access to the plaintext. While the algorithm is still not efficient enough for practical applications, homomorphic encryption has potential in many areas such as voting, storage of sensitive personal information, and analyzing demo-graphical data. In 2009, Gentry proposed the first plausible algorithm for fully homomorphic encryption, and various improvements have been built upon this result, significantly increasing the efficiency of homomorphic encryption. In Gentry’s original implementation, lattice-based cryptography is used as a basis of the Homomorphic encryption scheme. Lattice-based cryptography still lies at the heart of many fully homomorphic encryption schemes. In this report, we build on previous VIP works and illustrate various lattice-based encryption schemes, and briefly describe how Gentry used lattice-based cryptography to construct the first fully homomorphic encryption scheme. In addition, this sub-team hopes the incoming VIP sub-teams would make use of this report and expand upon our research into homomorphic encryption.
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    Loss-Tolerant and Secure Embedded Computing via Inscrutable Instruction-Set Architectures (I²SA)
    (Georgia Institute of Technology, 2004) Mooney, Vincent John, III ; Palem, Krishna V. ; Wunderlich, Richard B. ; College of Computing
    In short, we examine secure computing where a microprocessor reads, writes and executes operations ideally in an inscrutable domain. The goal is to provide methods and implementations for computation where data never leave the inscrutable domain in which they reside; the intended effect is twofold. The first intended effect is that any transmissions between computing media using our approach would be unbreakable in any reasonable amount of time; i.e., intercepted instructions and/or data would be meaningless to the unauthorized interceptor. The second intended effect is that, as a result of embedded computing platforms realized using inscrutable computing elements, any loss of equipment utilizing such computing hardware would not be very meaningful to the recoverer: we refer to this as loss tolerance.
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    The Sleepy Keeper Approach: Methodology, Layout and Power Results for a 4-bit Adder
    (Georgia Institute of Technology, 2006) Kim, Se Hun ; Mooney, Vincent John, III ; Center for Experimental Research in Computer Systems
    For the most recent CMOS feature sizes (e.g., 90nm and 65nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. We propose a novel approach, named "sleepy keeper", which reduces leakage current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus two additional transistors - driven by a gate's already calculated output - to save state during sleep mode. Dual Vth values can be applied to sleepy keeper in order to dramatically reduce subthreshold leakage current. In short, like the sleepy stack approach, sleepy keeper achieves leakage power reduction equivalent to the sleep and zigzag approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered). Based on experiments with a 4-bit adder circuit, sleepy keeper approach achieves up to 48% less ! delay and 49% less area than the sleepy stack approach. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 21% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon in a VLSI designer's arsenal.
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    Instruction-level Reverse Execution for Debugging
    (Georgia Institute of Technology, 2002) Akgul, Tankut ; Mooney, Vincent John, III ; College of Computing
    Reverse execution provides a programmer with the ability to return a program to a previous state in its execution history. The ability to execute a program in reverse is advantageous for shortening software development time. Conventional techniques for reverse execution rely on saving a state into a record before the state is destroyed. State saving introduces both memory and time overheads during forward execution. Our proposed method introduces a reverse execution methodology at the assembly instruction level with low memory and time overheads. The methodology generates from a program a reverse program by which a destroyed state is almost always regenerated rather than being restored from a record. This significantly reduces state saving. The methodology has been implemented on a PowerPC processor with a custom made debugger. As compared to previous work using state saving techniques, the experimental results show 2.5X to 400X memory overhead reduction for the tested benchmarks. Furthermore, the results with the same benchmarks show an average of 4.1X to 5.7X reduction in execution time overhead.
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    Automated Bus Generation for Multiprocessor SoC Design
    (Georgia Institute of Technology, 2002) Ryu, Kyeong Keol ; Mooney, Vincent John, III ; College of Computing
    The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis tool (BusSyn) uses this methodology to generate five different bus systems as examples: Bi-FIFO Bus Architecture (BFBA), Global Bus Architecture Version I (GBAVI), Global Bus Architecture Version III (GBAVIII), Hybrid bus architecture (Hybrid) and Split Bus Architecture (SplitBA). We verify and evaluate the performance of each bus system in the context of three applications: an Orthogonal Frequency Division Multiplexing (OFDM) wireless transmitter, an MPEG2 decoder and a database example. This methodology gives the designer a great benefit in fast design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types and software programming style. In this paper, we show that BusSyn can generate buses that achieve superior performance when compared to a simple General Global Bus Architecture (GGBA) (e.g., 41% reduction in execution time in the case of a database example). In addition, the bus architecture generated by BusSyn is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.
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    Round-robin Arbiter Design and Generation
    (Georgia Institute of Technology, 2002) Shin, Eung Seo ; Mooney, Vincent John, III ; Riley, George F. ; College of Computing
    In this paper, we introduce a Roundrobin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of bus masters for both on-chip and off-chip buses specified by the user of RAG. RAG can also generate a distributed and parallel hierarchical Switch Arbiter (SA). The first contribution of this paper is the automated generation of a round-robin token passing BA to reduce time spent on arbiter design. The generated arbiter is fair, fast, and has a low and predictable worst-case wait time. The second contribution of this paper is the design and integration of a distributed fast arbiter, e.g., for a terabit switch, based on 4x4 and 2x2 switch arbiters (SAs). Using a .25 TSMC standard cell library from LEDA Systems [11, 15], we show the arbitration time of a 256x256 SA for a terabit switch and demonstrate that the SA generated by RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design. Furthermore, our generated SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by a factor of 1.9X and 2.4X, respectively.
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    Pareto Points in SRAM Design Using the Sleepy Stack Approach
    (Georgia Institute of Technology, 2005) Park, Jun Cheol ; Mooney, Vincent John, III ; College of Computing
    Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultra-low leakage SRAM design which we call "sleepy stack SRAM." Unlike many other previous approaches, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6T SRAM cell with high-V[subscript th] transistors, the sleepy stack SRAM cell with 1.5xV[subscript th] at 110-degree C achieves more than 5X leakage power reduction at a cost of 31% delay increase and 113% area increase. Alternatively, by widening wordline pass transistors, the sleepy stack SRAM cell can match the delay of the high-V[subscript th] 6T SRAM and still achieve 2.5X leakage power reduction at a cost of a 139% area penalty.
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    Timing Analysis for Preemptive Multi-tasking Real-Time Systems with Caches
    (Georgia Institute of Technology, 2004) Tan, Yudong ; Mooney, Vincent John, III ; College of Computing
    In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task in a preemptive multi-tasking single-processor real-time system with an L1 cache. The approach combines inter-task cache eviction analysis and intra-task cache access analysis to estimate the number of cache lines that can possibly be evicted by the preempting task and also be accessed again by the preempted task after preemptions (thus requiring the preempted task to reload the cache line(s)). This cache reload delay caused by preempting tasks is then incorporated into WCRT analysis. Two sets of applications are used to test our approach. Each set of applications contains three tasks. The experimental results show that our approach can tighten the WCRT estimate by 38% (1.6X) to 56% (2.3X) over prior state-of-the-art.
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    An O(NIN(M,N)) Parallel Deadlock Detection Algorithm
    (Georgia Institute of Technology, 2003) Lee, Jaehwan ; Mooney, Vincent John, III ; College of Computing
    This paper presents a novel Parallel Deadlock Detection Algorithm (PDDA) and its hardware implementation, Deadlock Detection Unit (DDU). PDDA uses simple boolean representations of request, grant and no activity so that the hardware implementation of PDDA becomes easier and operates faster. We prove that the DDU has a worst-case run-time of 2 x min(m, n) - O(min(m,n)), where m is the number of resources and n is the number of processes. Previous algorithms in software, by contrast, have O(m x n) run-time complexity. We also prove the correctness of PDDA and the DDU. The DDU reduces deadlock detection time by 99.9%, (i.e., 1000X) or more compared to software implementations of deadlock detection algorithms. An experiment involving a practical situation that employs the DDU showed that the time measured from application initialization to deadlock detection was reduced by 46% compared to detecting deadlock in software.
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    Task Scheduling for Control Oriented Requirements for Cyber-Physical Systems
    (Georgia Institute of Technology, 2008-12) Zhang, Fumin ; Szwaykowska, Klementyna ; Wolf, Wayne ; Mooney, Vincent John, III ; Institute for Robotics and Intelligent Machines ; Georgia Institute of Technology. Center for Robotics and Intelligent Machines
    The wide applications of cyber-physical systems (CPS) call for effective design strategies that optimize the performance of both computing units and physical plants. We study the task scheduling problem for a class of CPS whose behaviors are regulated by feedback control laws. We codesign the control law and the task scheduling algorithm for predictable performance and power consumption for both the computing and the physical systems. We use a typical example, multiple inverted pendulums controlled by one processor, to illustrate our method.