Title:
Automated Bus Generation for Multiprocessor SoC Design
Automated Bus Generation for Multiprocessor SoC Design
Author(s)
Ryu, Kyeong Keol
Mooney, Vincent John, III
Mooney, Vincent John, III
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Abstract
The performance of a system, especially a multiprocessor system,
heavily depends upon the efficiency of its bus architecture.
This paper presents a methodology to generate a custom bus system
for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis
tool (BusSyn) uses this methodology to generate five different
bus systems as examples: Bi-FIFO Bus Architecture (BFBA),
Global Bus Architecture Version I (GBAVI), Global Bus
Architecture Version III (GBAVIII), Hybrid bus architecture
(Hybrid) and Split Bus Architecture (SplitBA). We verify
and evaluate the performance of each bus system in the context
of three applications: an Orthogonal Frequency Division
Multiplexing (OFDM) wireless transmitter, an MPEG2 decoder
and a database example. This methodology gives the designer
a great benefit in fast design space exploration of bus
architectures across a variety of performance impacting
factors such as bus types, processor types and software
programming style. In this paper, we show that BusSyn can
generate buses that achieve superior performance when
compared to a simple General Global Bus Architecture (GGBA)
(e.g., 41% reduction in execution time in the case of a
database example). In addition, the bus architecture generated
by BusSyn is designed in a matter of seconds instead of weeks
for the hand design of a custom bus system.
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Date Issued
2002
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471908 bytes
Resource Type
Text
Resource Subtype
Technical Report