Round-robin Arbiter Design and Generation
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Abstract
In this paper, we introduce a Roundrobin Arbiter Generator (RAG)
tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is
able to handle the exact number of bus masters for both on-chip and off-chip
buses specified by the user of RAG. RAG can also generate a distributed and
parallel hierarchical Switch Arbiter (SA). The first contribution of this
paper is the automated generation of a round-robin token passing BA to
reduce time spent on arbiter design. The generated arbiter is fair, fast,
and has a low and predictable worst-case wait time. The second contribution
of this paper is the design and integration of a distributed fast arbiter,
e.g., for a terabit switch, based on 4x4 and 2x2 switch arbiters (SAs).
Using a .25 TSMC standard cell library from LEDA Systems [11, 15], we show
the arbitration time of a 256x256 SA for a terabit switch and demonstrate
that the SA generated by RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design.
Furthermore, our generated SA performs better than the Ping-Pong Arbiter and
Programmable Priority Encoder by a factor of 1.9X and 2.4X, respectively.
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Date
2002
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Technical Report