Title:
On the Architectural Requirements for Efficient Execution of Graph Algorithms
On the Architectural Requirements for Efficient Execution of Graph Algorithms
Author(s)
Bader, David A.
Cong, Guojing
Cong, Guojing
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Abstract
Combinatorial problems such as those from graph theory pose serious challenges for
parallel machines due to non-contiguous, concurrent accesses to global data structures
with low degrees of locality. The hierarchical memory systems of symmetric multiprocessor (SMP) clusters optimize for local, contiguous memory accesses, and so are
inefficient platforms for such algorithms. Few parallel graph algorithms outperform
their best sequential implementation on SMP clusters due to long memory latencies
and high synchronization costs. In this paper, we consider the performance and scalability of two graph algorithms, list ranking and connected components, on two classes
of shared-memory computers: symmetric multiprocessors such as the Sun Enterprise
servers and multithreaded architectures (MTA) such as the Cray MTA-2. While previous studies have shown that parallel graph algorithms can speedup on SMPs, the
systems' reliance on cache microprocessors limits performance. The MTA's latency
tolerant processors and hardware support for fine-grain synchronization makes performance a function of parallelism. Since parallel graph algorithms have an abundance
of parallelism, they perform and scale significantly better on the MTA. We describe
and give a performance model for each architecture. We analyze the performance of
the two algorithms and discuss how the features of each architecture affects algorithm
development, ease of programming, performance, and scalability.
Sponsor
This work was supported in part by NSF Grants CAREER ACI-00-93039, ITR ACI-00-81404, DEB-99-
10123, ITR EIA-01-21377, Biocomplexity DEB-01-20709, DBI-0420513, ITR EF/BIO 03-31654; and DARPA
Contract NBCH30390004.
Date Issued
2006-02-25
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Technical Report