College of Computing Technical Report Series

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Now showing 1 - 10 of 506
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    Contech: A Tool for Analyzing Parallel Programs
    (Georgia Institute of Technology, 2013) Railing, Brian P. ; Hein, Eric R. ; Vassenko, Phillip ; Conte, Thomas M. ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. School of Computer Science
    The behavior and structure of a shared-memory parallel program can be characterized by a task graph that encodes the instructions, memory accesses, and dependencies of each piece of parallel work. Task graphs are not specific to one threading library or target architecture. The Contech analysis framework provides the means for generating and analyzing task graphs that enable computer architects and programmers to gain a deeper understanding of parallel programs.
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    Multimodal Analogies in Modelling and Design
    (Georgia Institute of Technology, 2005) Yaner, Patrick W.
    Drawings, on the one hand, and teleological models, on the other, are two ways of understanding and communicating design information. Drawing on previous work, Structure-Behavior-Function (SBF) theory claims that teleological knowledge is comprised of three basic kinds of knowledge: structural knowledge, behavioral knowledge, and functional knowledge. However, the design task, in practice, revolves around draw- ings. For example, Computer-Aided Design (CAD) software manipulates and produces drawings, and to produce a design is to produce a set of documents that primarily consists of drawings of that design. And yet, drawings can, at best, represent only structural knowledge, and even that incompletely, as components' roles in the design are not and cannot be determined solely by the drawing. Two questions motivate this research: (1) what role, precisely, do drawings place in the design process? and (2) how can we enhance CAD tools to make more direct use of teleological knowledge? This work explores two problems: model construction and design generation. The problem of constructing an SBF model of a mechanical device from a drawing can be solved in a robust and tractable way using analogical reasoning, by reasoning from visual and topological differences to structural, causal, and functional differences in models. Patterns of adaptation and transfer can be captured by Generic Visual Teleological Mechanisms (GVTMs), generic patterns of adaptation that capture particular abstractions. Likewise, the problem of design generation, proceeding from a functional specification to a drawing associated with a complete SBF model, can be solved in a robust and tractable manner using analogical reasoning from functional differences to structural and behavioral differences in models, and ultimately to visual differences in drawings. Patterns of adaptation, here, can be effectively solved by Generic Teleological Drawing Mechanisms (GTDMs), capturing similar patterns to GVTMs, but proceeding from function to drawing instead of the reverse. Both are essentially constructive, and together help to elucidate the nature and interplay between visual structure and topology, on the one hand, and causality and teleology, on the other hand, in modelling and design.
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    Data Remapping for Design Space Optimization of Embedded Cache Systems
    (Georgia Institute of Technology, 2002) Palem, Krishna V. ; Rabbah, Rodric Michel
    In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, (ii) fully automated and (iii) applicable in the context of pointer-centric programming languages with dynamic memory allocation support. All previous work in this area lacks one or more of these features. We go on to show that this algorithm impacts the design and usage of embedded systems in two significant ways. First, we show that by virtue of locality enhancements via data remapping, our approach halves the amount of cache memory needed to support a specified performance goal. While cache systems are very desirable from a performance standpoint, cost considerations have always limited their use in the context of embedded designs. However, we have shown that remapping can significantly lower cache needs, and thus it can be a key step in optimizing the memory needs during design-space exploration of embedded systems. To help achieve this goal, we identify a range of metrics for quantifying the costs associated with popular notions of locality, prefetching, regularity of memory access and others. These metrics can serve as the quantitative foundations of a design space exploration system in which remapping can play a crucial role for optimizing the costs associated with the cache subsystem. Second, for several COTS microprocessors with a fixed cache architecture, such as the Pentium and UltraSparc, we show that remapping can achieve a performance improvement of 20% on the average. In addition, for a parametric research HPL-PD microprocessor, which characterizes the new Itanium machines, we achieve a performance improvement of 28% on average. All of our results are achieved using applications from the DIS, OLDEN and SPEC2000 suites of integer and floating point benchmarks.
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    On Resource Management and QoS Guarantees For Long Range Dependent Traffic
    (Georgia Institute of Technology, 1994) Adas, Abdelnaser M. ; Mukherjee, Amarnath
    It has been known for several years now that variable-bit-rate video sources are strongly auto-correlated. Recently, several studies have indicated that the resulting stochastic processes exhibit long-range dependence properties. This implies that large buffers at intermediate switching points may not provide adequate delay performance for such classes of traffic in Broadband packet-switched networks (such as ATM). Given these observations, and the need to provide guaranteed maximum-delay and delay-jitter bounds, and low cell-loss probabilities to applications, the solution appears to be (a) allocating higher rates if the distribution tails are large, (b) using multiplexing to narrow these tails, (c) applying a per circuit frame-clock in conjunction with an active cell-discard strategy to deal with long-range dependence. Strategy (c) is a version of the Stop and Go Stop queuing that does not require tight deterministic rate specifications, but provides maximum-delay and delay-jitter bounds over multiple hops as in the original proposal. The combined strategy is a hybrid between packet switching and circuit switching technology. This research was supported in part by the National Science Foundation under grant NCR-9396299. This is a revised and extended version of a paper that is to be presented at the IEEE Infocom '95 Conference in Boston in April 1995.
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    Boosting Metacognition via Metacognitive Wrapper
    (Georgia Institute of Technology, 2018-04) Nenkov, Andrey N. ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. School of Computer Science
    Metacognition is often described as thinking about thinking and is tightly related to academic success and intelligence. Very specific techniques exist for metacognition to be put in practice and improved. This paper introduces a proof-of-concept system to promote metacognitive skills. Its main purpose is to make learners more effective.
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    Reasoning About Conditional Progress Properties
    (Georgia Institute of Technology, 1994) Calvert, Kenneth L.
    In some otherwise attractive formalisms, it can be difficult or even impossible to specify progress in such a way that a component of a distributed system can be proved correct independent of its environment. This problem arises because the nested dependencies between the component and its environment cannot be conveniently expressed in the formalism. A typical example is a communication protocol, which is supposed to provide reliable data transfer even over channels that are unboundedly lossy: the channels only deliver messages if the protocol transmits them often enough, while the protocol only guarantees reliable service if the channels deliver sufficiently many messages. This paper investigates the extent to which such progress specifications can be dealt with using predicate calculus and a single temporal operator (leads-to) having a simple proof theory. It turns out that under the proper semantic interpretation, many progress specifications expressing complex dependences can be represented using certain boolean combinations of leads-to properties. By adding two simple inference rules to an existing proof theory, we obtain a (relatively) complete theory for a large class of conditional progress properties, without the complexity of the full temporal logic; such a theory can be used with various compositional specification formalisms. Based on the results, an approach to specification of protocol progress is outlined and illustrated with an example.
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    A Comparative Study of Distributed Shared Memory System Design Issues
    (Georgia Institute of Technology, 1994) Mohindra, Ajay ; Ramachandran, Umakishore
    In this research the various issues that arise in the design and implementation of distributed shared memory (DSM) systems are examined. This work has been motivated by two observations: distributed systems will continue to become popular, and will be increasingly used for solving large computational problems; and shared memory paradigm is attractive for programming large distributed systems because it offers a natural transition for a programmer from the world of uniprocessors. The goal of this work is to identify a set of system issues in applying the shared memory paradigm to a distributed system, and evaluate the effects of the ensuing design alternatives on the performance of DSM systems. The design alternatives have been evaluated in two steps. First, we undertake a detailed measurement-based study of a distributed shared memory implementation on the Clouds distributed operating system towards understanding the system issues. Second, a simulation-based approach is used to evaluate the system issues. A new workload model that captures the salient features of parallel and distributed programs is developed and used to drive the simulator. The key results of the research are that the choice of the memory model and coherence protocol does not significantly influence the system performance for applications exhibiting high computation granularity and low state-sharing; weaker memory models become significant for large-scale DSM systems; the unit of coherence maintenance depends on a set of parameters including the overheads for servicing data requests as well as the speed of data transmission on the network; and the design of miscellaneous system services (such as synchronization and data servers) can play an important role in the performance of DSM systems.
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    Project Livermore: 3D Simulation of Human Anatomy and Patient Education on Medical Conditions
    (Georgia Institute of Technology, 2018-04) Lam, Andrew ; Lockett, Cheryl ; Reina, Jennifer ; Syed, Rafay ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. School of Computer Science
    Project Livermore is a development project intended to address the issue of providing patients with timely and engaging personalized educational materials consistent with a diagnosis they may have received. This paper is intended to demonstrate a proof-of-concept tool to facilitate the dissemination of educational materials by way of a standards-based inter-operable tool whereby a patient is able to observe and manipulate a 3D model based on their diagnosis, observe disease progression, and read supporting literature. The tool is designed around a problem-based learning pedagogy that uses simulation-based learning to promote understanding.
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    Round-robin Arbiter Design and Generation
    (Georgia Institute of Technology, 2002) Shin, Eung Seo ; Mooney, Vincent John, III ; Riley, George F.
    In this paper, we introduce a Roundrobin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of bus masters for both on-chip and off-chip buses specified by the user of RAG. RAG can also generate a distributed and parallel hierarchical Switch Arbiter (SA). The first contribution of this paper is the automated generation of a round-robin token passing BA to reduce time spent on arbiter design. The generated arbiter is fair, fast, and has a low and predictable worst-case wait time. The second contribution of this paper is the design and integration of a distributed fast arbiter, e.g., for a terabit switch, based on 4x4 and 2x2 switch arbiters (SAs). Using a .25 TSMC standard cell library from LEDA Systems [11, 15], we show the arbitration time of a 256x256 SA for a terabit switch and demonstrate that the SA generated by RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design. Furthermore, our generated SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by a factor of 1.9X and 2.4X, respectively.
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    Fishing for Phishing from the Network Stream
    (Georgia Institute of Technology, 2008) Ramachandran, Anirudh ; Feamster, Nick ; Krishnamurthy, Balachander ; Spatscheck, Oliver ; Van der Merwe, Jacobus ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. School of Computer Science ; AT&T Labs Research
    Phishing is an increasingly prevalent social-engineering attack that attempts identity theft using spoofed Web pages of legitimate organizations. Unfortunately, current phishing detection methods are neither complete nor responsive because they rely on user reports, and many also require clientside software. Anti-phishing techniques could be more effective if they (1) could detect phishing attacks automatically from the network traffic; (2) could operate without cooperation from end-users. This paper performs a preliminary study to determine the feasibility of detecting phishing attacks in real-time, from the network traffic stream itself. We develop a model to identify the stages where in-network phishing detection is feasible and the data sources that can be analyzed to provide relevant information at each stage. Based on this model, we develop and evaluate a detection method based on features that exist in the network traffic it- self and are correlated with confirmed phishing attacks.