Person:
Swaminathan, Madhavan

Permanent Link
https://hdl.handle.net/1853/72393
Associated Organization(s)
ORCID
ArchiveSpace Name Record

Filters

7
7
7
Reset filters

Settings
Author: Swaminathan, Madhavan × search.filters.applied.f.resourcesubtype: Technical Report ×

Publication Search Results

Now showing 1 - 7 of 7
  • Thumbnail Image
    Item
    Development of compliant free-standing structures for sub 32-nm multi-core ICs
    (Georgia Institute of Technology, 2012-11) Sitaraman, Suresh K. ; Swaminathan, Madhavan
    With the introduction of on-chip low-K dielectric materials, it is increasingly important to reduce on-chip stresses so that the low-K dielectric material will not crack or delaminate. One way to reduce the thermo-mechanical stresses is to introduce compliant structures between the die and the substrate and thus to decouple the die from the substrate. Decoupling the die from the substrate or the substrate from the board by means of mechanically compliant interconnects will reduce stresses created by the coefficient of thermal expansion mismatch. A decoupled diesubstrate or substrate-board interface will allow the different components to expand or contract differently without inducing high stresses in the components. In this work, we report the design, fabrication, modeling, and characterization of innovative multi-path fan-shaped off-chip compliant interconnects. The proposed interconnects can be fabricated at the wafer-level and are cost-effective, can be of fine pitch and scalable, and will have redundant electrical paths.
  • Thumbnail Image
    Item
    Modeling and co-simulation of power distribution networked in digitaland mix
    (Georgia Institute of Technology, 2006-01-31) Swaminathan, Madhavan
  • Thumbnail Image
    Item
    Modeling of power supply noise in FPGA
    (Georgia Institute of Technology, 2004-09-01) Swaminathan, Madhavan
  • Thumbnail Image
    Item
    Congestion and Power Integrity Aware Placement and Routing for 3D Packaging
    (Georgia Institute of Technology, 2004-04-23) Minz, Jacob Rajkumar ; Choi, Jinwoo ; Swaminathan, Madhavan ; Lim, Sung Kyu
    One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion trade-off. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.
  • Thumbnail Image
    Item
    The design of the power delivery system for next generation gigahertz packages
    (Georgia Institute of Technology, 2003-01-31) Swaminathan, Madhavan
  • Thumbnail Image
    Item
    Chip-Package Co-Design Methodology for Integrated RF Microsystems
    (Georgia Institute of Technology, 2001-09-15) Swaminathan, Madhavan
  • Thumbnail Image
    Item
    Embedded design of rf components in low temperature cofired ceramic (LTCC)
    (Georgia Institute of Technology, 1998) Swaminathan, Madhavan