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Lim, Sung Kyu

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Author: Lim, Sung Kyu × End date: 2004 × Start date: 2004 × Item Type: Publication × Type: Text ×

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Now showing 1 - 4 of 4
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    Wire Congestion And Thermal Aware Global Placement For 3D VLSI Circuits
    (Georgia Institute of Technology, 2004-05-26) Balakrishnan, Karthik ; Nanda, Vidit ; Easwar, Siddharth Sangam ; Lim, Sung Kyu
    The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce global the temperature gradient and local and global congestions of 3D circuit designs without compromising total intra-layer wirelength or inter-layer via count. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local wire congestion and power dissipation. Then, we perform simulated annealing with a full-length thermal analysis to reduce the circuit's global congestion and thermal gradient. Experimental results show that when compared to the standard mincut approach, our thermal gradient and local congestion are reduced by 25% each, global congestion is reduced by over 7%. Moreover, we only see a 10% increase in the wiring length and the number of vias required.
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    Channel and Pin Assignment for Three Dimensional Packaging Routing
    (Georgia Institute of Technology, 2004-05-24) Minz, Jacob Rajkumar ; Lim, Sung Kyu
    Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. The contribution of this work is threefold: (i) formulation of the new 3-dimensional global routing problem, (ii) a new routing flow that considers the various design constraints unique to SOP, and (iii) a global router for the technology. Our related experimental results demonstrate the effectiveness of our algorithm.
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    Congestion and Power Integrity Aware Placement and Routing for 3D Packaging
    (Georgia Institute of Technology, 2004-04-23) Minz, Jacob Rajkumar ; Choi, Jinwoo ; Swaminathan, Madhavan ; Lim, Sung Kyu
    One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion trade-off. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.
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    Thermal-aware 3D Microarchitectural Floorplanning
    (Georgia Institute of Technology, 2004) Ekpanyapong, Mongkol ; Healy, Michael ; Ballapuram, Chinnakrishnan S. ; Lim, Sung Kyu ; Lee, Hsien-Hsin Sean ; Loh, Gabriel H.
    Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper pipelines and higher clock frequency. The move to 3D ICs will also likely be used to further shorten wirelength. This will cause thermal issues to become a major bottleneck to performance improvement. In this paper we propose a floorplanning algorithm which takes into consideration both thermal issues and profile weighted wirelength using mathematical programming. Our profile-driven objective improves performance by 20% over wirelength-driven. While the thermal-driven objective improves temperature by 24% on average over the profile-driven case.