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Lim,
Sung Kyu
Lim,
Sung Kyu
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ItemImpact of Multi-level Clustering on Performance Driven Global Placement(Georgia Institute of Technology, 2003) Balakrishnan, Karthik ; Nanda, Vidit ; Ekpanyapong, Mongkol ; Lim, Sung KyuDelay and wirelength minimization continue to be important objectives in the design of high-performance computing systems. For large-scale circuits, the clustering process becomes essential for reducing the problem size. However, to the best of our knowledge, there is no study about the impact of multi-level clustering on performance-driven global placement. In this paper, five clustering algorithms including the quasi-optimal retiming delay driven PRIME and the cutsize-driven ESC have been considered for their impact on state-of-the-art mincut based global placement. Results show that minimizing cutsize or wirelength during clustering typically results in significant performance improvements.
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ItemProfile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design(Georgia Institute of Technology, 2003) Ekpanyapong, Mongkol ; Minz, Jacob Rajkumar ; Watewai, Thaisiri ; Lee, Hsien-Hsin Sean ; Lim, Sung KyuAs process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying the performance scalability substantially. An effective floorplanning algorithm can no longer ignore the information of dynamic communication patterns of applications. In this paper, using the profile information acquired at the architecture/microarchitecture level, we propose a "profile-guided microarchitectural floorplanner" that considers both the impact of wire delay and the architectural behavior, namely the inter-module communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on our simulation results, the profile-guided method shows a 5% to 40% IPC improvement when clock frequency is fixed. From the perspective of instruction throughput (in BIPS), our floorplanner is much more scalable than a conventional wire length based floorplanner.
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ItemCongestion-Driven Global Placement for Three Dimensional VLSI Circuits(Georgia Institute of Technology, 2003) Nanda, Vidit ; Balakrishnan, Karthik ; Ekpanyapong, Mongkol ; Lim, Sung KyuThe recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, the problem of thermal dissipation is magnified due to the nature of these layered technologies. In this paper, we develop techniques to reduce both the local and global congestions of 3D circuit designs in order to alleviate thermal issues. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local congestion. Then, we perform simulated annealing to reduce the circuit's global congestion. Experimental results show that our local congestion is reduced by an average of over 44% and global congestion is reduced by over 16%. Moreover, we only see an 11% increase in the wiring length and the number of vias required.
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ItemSimultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming(Georgia Institute of Technology, 2003) Ekpanyapong, Mongkol ; Lim, Sung KyuDelay minimization and power minimization are two important objectives in the design of the high-performance, portable, and wireless computing and communication systems. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a unified framework for multi-level partitioning and floorplanning with retiming, targeting simultaneous delay and power optimization. We first discuss the importance of retiming delay and visible power as opposed to the conventional static delay and total power for sequential circuits. Then we propose GEO-PD algorithm for simultaneous delay and power optimization and provide smooth cutsize, wirelength, power and delay tradeoff. In GEO-PD, we use retiming based timing analysis and visible power analysis to identify timing and power critical nets and assign proper weights to them to guide the multi-level optimization process. In general, timing and power analysis are done at the original netlist while a recursive multi-level approach performs partitioning and floorplanning on the sub-netlist as well as its coarsened representations. We show an effective way to translate the timing and power analysis results from the original netlist to a coarsened sub-netlist for effective multi-level delay and power optimization. To the best of our knowledge, this is the first paper addressing simultaneous delay and power optimization in multi-level partitioning and floorplanning.
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ItemPerformance-driven Global Placement via Adaptive Network Characterization(Georgia Institute of Technology, 2003) Ekpanyapong, Mongkol ; Lim, Sung KyuDelay minimization continues to be an important objective in the design of high-performance computing system. In this paper, we present an effective methodology to guide the delay optimization process of the mincut-based global placement via adaptive sequential network characterization. The contribution of this work is the development of a fully automated approach to determine critical parameters related to performance-driven multi-level partitioning-based global placement with retiming. We validate our approach by incorporating this adaptive method into a state-of-the-art global placer GEO. Our A-GEO, the adaptive version of GEO, achieves 67% maximum and 22% average delay improvement over GEO.