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Chatterjee, Abhijit

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Adaptive FPGA-based Test Module

2013-05-30 , Chatterjee, Abhijit , Keezer, David C.

The objective of the project is to develop methods and electronics for testing multi-GHz digital components (such as DDR memories), using low-cost methods based on state-of-the-art field programmable gate arrays (FPGAs). A further objective is to incorporate the means for the test electronics to “self-monitor” its own performance, and to “adapt” its behavior (performance) in order to optimize the quality of the test signals. Therefore this project seeks to realize two major benefits as compared to traditional testing methods: (1) lower test equipment cost and (2) improved test signal quality (especially for high-speed signals). This report describes the activities and preliminary results obtained during the first six months of this project.

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Final report: optimal linearity testing of Sigma-Delta based incremental ADCs using restricted code measurements

2010-05-31 , Chatterjee, Abhijit , Kook, S. , Gomes, A. , Jin, L. , Wheelright, D.

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Targeting multi-core clock performance gains: vertically integrated adaptation and prototyping

2012-06 , Chatterjee, Abhijit

A low cost post-manufacturing testing and speed tuning methodology is proposed in a multi-processor system. The goal of this research is to develop a methodology that allows the “safe” speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures.

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Optimal linearity testing of sigma-delta based incremental ADCs using restricted code measurements

2010-11 , Chatterjee, Abhijit , Kook, S. , Gomes, A. , Jin, L. , Wheelright, D.

Linearity testing of high-precision (beyond 20-bit resolution) Analog-to-Digital converters (ADCs) is extremely expensive due to the large number of codes (>16 million for a 24-bit converter) that need to be tested and the associated low data rates making traditional histogram based testing infeasible. Industry often performs linearity test for such high-precision data converters with significantly reduced numbers of code measurements during production test. Given a specified allowed number of code measurements, the problem is to determine the requisite code points that result in the highest failure coverage. In this report, a methodology and tools for analyzing the “goodness” of a particular choice of test code points versus another is described. A least squares based polynomial fitting approach using measurements made at selected test code points is used to characterize the transfer function of the ADC for INL (Integral Nonlinearity) error. In addition, the characteristics of devices that may escape from the proposed approach (test escapes) are revealed for the specified test via an optimization based search technique. Software simulations are performed to study and validate the proposed methodology.

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