Title:
Targeting multi-core clock performance gains: vertically integrated adaptation and prototyping
Targeting multi-core clock performance gains: vertically integrated adaptation and prototyping
Author(s)
Chatterjee, Abhijit
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Abstract
A low cost post-manufacturing testing and speed tuning methodology is proposed in a multi-processor system. The goal of this research is to develop a methodology that allows the “safe” speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures.
Sponsor
National Science Foundation (U.S.)
Date Issued
2012-06
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Resource Type
Text
Resource Subtype
Technical Report