Title:
Compiler Assisted Dynamic Management of Registers for Network Processors
Compiler Assisted Dynamic Management of Registers for Network Processors
| dc.contributor.author | Collins, Ryan | |
| dc.contributor.author | Alegre, Fernando | |
| dc.contributor.author | Zhuang, Xiaotong | |
| dc.contributor.author | Pande, Santosh | |
| dc.date.accessioned | 2006-02-07T20:12:39Z | |
| dc.date.available | 2006-02-07T20:12:39Z | |
| dc.date.issued | 2005 | |
| dc.description.abstract | Modern network processors such as the Intel IXP family hide the latency of slow instructions by supporting multiple threads of execution. Context switches in the IXP architecture are designed to be very fast. However, the low overhead is partly achieved by leaving register management to programs, with little support from the hardware. The complexity of the multi-engine, multi-threaded environment makes manual register management a daunting task, which is better left to the compiler. However, a purely static analysis may not be able to achieve full utilization of the register file due to conservative estimates of liveness. A register that is live across a context switch point must be considered live for the duration of all other threads, and so it must be assumed to be unavailable to other threads. In addition, aliasing further reduces the effectiveness of static analysis. The net effect is a large number of idle cycles that are still present after static optimization. We propose a dynamic solution that requires minimal software and hardware support. On the software side, we take a pre-allocated binary file and annotate the potential context switch instructions with information about the dead registers. On the hardware side, we try to rename all transfer registers and addresses to dead general purpose registers and update the vector of used registers. We then replace the long-latency memory instructions with fast move instructions in the architecture using the dynamic context. The results show up to 51% reduction in idle cycles and up to 14% increase in the throughput for hand coded applications. | en |
| dc.format.extent | 274763 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/7713 | |
| dc.language.iso | en_US | en |
| dc.publisher | Georgia Institute of Technology | en |
| dc.relation.ispartofseries | CERCS;GIT-CERCS-05-21 | en |
| dc.subject | Register allocation during execution | |
| dc.subject | IXP architecture | |
| dc.subject | Dynamic context | |
| dc.subject | Aliased memory | |
| dc.subject | Latency | |
| dc.subject | Throughputs | |
| dc.subject | Multiple threads of execution | |
| dc.title | Compiler Assisted Dynamic Management of Registers for Network Processors | en |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.author | Pande, Santosh | |
| local.contributor.corporatename | Center for Experimental Research in Computer Systems | |
| local.relation.ispartofseries | CERCS Technical Report Series | |
| relation.isAuthorOfPublication | 6239fe5b-32c4-4067-9614-1ccca3374873 | |
| relation.isOrgUnitOfPublication | 1dd858c0-be27-47fd-873d-208407cf0794 | |
| relation.isSeriesOfPublication | bc21f6b3-4b86-4b92-8b66-d65d59e12c54 |