Title:
Diagnosing performance bottlenecks in HPC applications
Diagnosing performance bottlenecks in HPC applications
| dc.contributor.advisor | Vuduc, Richard | |
| dc.contributor.author | Czechowski, Kenneth | |
| dc.contributor.committeeMember | Chow, Edmond | |
| dc.contributor.committeeMember | Kim, Hyesoon | |
| dc.contributor.committeeMember | Lee, Victor W. | |
| dc.contributor.committeeMember | Çatalyürek, Ümit V. | |
| dc.contributor.department | Computational Science and Engineering | |
| dc.date.accessioned | 2019-05-29T14:03:20Z | |
| dc.date.available | 2019-05-29T14:03:20Z | |
| dc.date.created | 2019-05 | |
| dc.date.issued | 2019-03-29 | |
| dc.date.submitted | May 2019 | |
| dc.date.updated | 2019-05-29T14:03:20Z | |
| dc.description.abstract | The software performance optimizations process is one of the most challenging aspects of developing highly performant code because underlying performance limitations are hard to diagnose. In many cases, identifying performance bottlenecks, such as latency stalls, requires a combination of fidelity and usability that existing tools do not provide: traditional performance models and runtime analysis lack the granularity necessary to uncover low-level bottlenecks; while, architectural simulations are too cumbersome and fragile to employ as a primary source of information. To address this need, we propose a performance analysis technique, called Pressure Point Analysis (PPA), which delivers the accessibility of analytical models with the precision of a simulator. The foundation of this approach is based on an autotuning-inspired technique that dynamically perturbs binary code (e.g., inserting/deleting instructions to affect utilization of functional units, altering memory access addresses to change cache hit rate, or swapping registers to alter instruction level dependencies) to then analyze the effects various perturbations have on the overall performance. When systematically applied, a battery of carefully designed perturbations, which target specific microarchitectural features, can glean valuable insight about pressure points in the code. PPA provides actionable information about hardware-software interactions that can be used by the software developer to manually tweak the application code. In some circumstances the performance bottlenecks are unavoidable, in which case this analysis can be used to establish a rigorous performance bound for the application. In other cases, this information can identify the primary performance limitations and project potential performance improvements if these bottlenecks are mitigated. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/61261 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | HPC | |
| dc.title | Diagnosing performance bottlenecks in HPC applications | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Vuduc, Richard | |
| local.contributor.corporatename | College of Computing | |
| local.contributor.corporatename | School of Computational Science and Engineering | |
| relation.isAdvisorOfPublication | e9a36794-e148-4304-8933-6ae0449c21d2 | |
| relation.isOrgUnitOfPublication | c8892b3c-8db6-4b7b-a33a-1b67f7db2021 | |
| relation.isOrgUnitOfPublication | 01ab2ef1-c6da-49c9-be98-fbd1d840d2b1 | |
| thesis.degree.level | Doctoral |