Title:
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
Author(s)
Krishnamurthy, Rajaram B.
Yalamanchili, Sudhakar
Schwan, Karsten
West, Richard
Yalamanchili, Sudhakar
Schwan, Karsten
West, Richard
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Abstract
ShareStreams (Scalable Hardware Architectures for
Stream Schedulers) is a canonical architecture for realizing
a range of scheduling disciplines. This paper discusses the design choices
and tradeoffs made in the development of a Endsystem/Host-based router
realization of the ShareStreams architecture. We evaluate the impact of
block decisions and aggregation on the ShareStreams architecture.
Using processor resources for queuing and data movement, and FPGA hardware for
accelerating stream selection and stream priority updates, ShareStreams can
easily meet the wire-speeds of 10Gbps links. This allows provision of
customized scheduling solutions and interoperability of scheduling
disciplines. FPGA hardware uses a single-cycle Decision block
to compare multiple stream attributes simultaneously for pairwise ordering
and a Decision block arrangement in a recirculating network to conserve
area and improve scalability. Our hardware implemented in the Xilinx Virtex
family easily scales from 4 to 32 stream-slots on a single chip. A running
FPGA prototype in a PCI card under systems software control can
provide scheduling support for a mix of EDF, static-priority and fair-share
streams based on user specifications and
meet the temporal bounds and packet-time requirements of multi-gigabit links.
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Date Issued
2003
Extent
197821 bytes
Resource Type
Text
Resource Subtype
Technical Report