Title:
Designing Irregular Parallel Algorithms With Mutual Exclusion and Lock-free Protocols
Designing Irregular Parallel Algorithms With Mutual Exclusion and Lock-free Protocols
| dc.contributor.author | Cong, Guojing | |
| dc.contributor.author | Bader, David A. | |
| dc.date.accessioned | 2007-05-15T18:13:19Z | |
| dc.date.available | 2007-05-15T18:13:19Z | |
| dc.date.issued | 2006-02-25 | |
| dc.description.abstract | Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an irregular application, fine-grained synchronization is one technique for managing the coordination of work; but in practice the actual performance for irregular problems depends on the input, the access pattern to shared data structures, the relative speed of processors, and the hardware support of synchronization primitives. In this paper, we focus on lock-free and mutual exclusion protocols for handling fine- grained synchronization. Mutual exclusion and lock-free protocols have received a fair amount of attention in coordinating accesses to shared data structures from concurrent processes. Mutual exclusion offers a simple programming abstraction, while lock-free data structures provide better fault tolerance and eliminate problems associated with critical sections such as priority inversion and deadlock. These synchronization protocols, however, are seldom used in parallel algorithm designs, especially for algorithms under the SPMD paradigm, as their implementations are highly hardware dependent and their costs are hard to characterize. Using graph-theoretic algorithms for illustrative purposes, we show experimental results on two shared-memory multiprocessors, the IBM pSeries 570 and the Sun Enterprise 4500, that irregular parallel algorithms with efficient fine-grained synchronization may yield good performance. | en |
| dc.description.sponsorship | This work was supported in part by NSF Grants CAREER ACI-00-93039, ITR ACI-00-81404, DEB-99- 10123, ITR EIA-01-21377, Biocomplexity DEB-01-20709, DBI-0420513, ITR EF/BIO 03-31654; and DARPA Contract NBCH30390004. | en |
| dc.identifier.uri | http://hdl.handle.net/1853/14378 | |
| dc.language.iso | en_US | en |
| dc.publisher | Georgia Institute of Technology | en |
| dc.relation.ispartofseries | CSE Technical Reports; GT-CSE-06-02 | en |
| dc.subject | Data structures | en |
| dc.subject | Fine-grained synchronization | en |
| dc.subject | Irregular parallel algorithms | en |
| dc.subject | Lock-free protocols | en |
| dc.subject | Mutual exclusion locks | en |
| dc.subject | Spanning tree algorithm | en |
| dc.subject | Spinlocks | en |
| dc.title | Designing Irregular Parallel Algorithms With Mutual Exclusion and Lock-free Protocols | en |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | College of Computing | |
| local.contributor.corporatename | School of Computational Science and Engineering | |
| local.relation.ispartofseries | College of Computing Technical Report Series | |
| local.relation.ispartofseries | School of Computational Science and Engineering Technical Report Series | |
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| relation.isOrgUnitOfPublication | 01ab2ef1-c6da-49c9-be98-fbd1d840d2b1 | |
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| relation.isSeriesOfPublication | 5a01f926-96af-453d-a75b-abc3e0f0abb3 |