Title:
Energy Introspector: Coordinated Architecture-Level Simulation of Processor Physics
Energy Introspector: Coordinated Architecture-Level Simulation of Processor Physics
| dc.contributor.author | Song, William J. | |
| dc.contributor.author | Mukhopadhyay, Saibal | |
| dc.contributor.author | Rodrigues, Arun | |
| dc.contributor.author | Yalamanchili, Sudhakar | |
| dc.contributor.corporatename | Georgia Institute of Technology. Center for Experimental Research in Computer Systems | en_US |
| dc.contributor.corporatename | Georgia Institute of Technology. School of Electrical and Computer Engineering | en_US |
| dc.contributor.corporatename | Sandia National Laboratories | en_US |
| dc.date.accessioned | 2015-06-09T14:37:12Z | |
| dc.date.available | 2015-06-09T14:37:12Z | |
| dc.date.issued | 2013 | |
| dc.description.abstract | Increased power and heat dissipation in microprocessors impose limitations on performance scaling. Power and thermal management techniques coupled with workload dynamics cause increasing spatiotemporal variations in electrical and thermal stresses. The coupling between various physical phenomena (e.g., power, temperature, reliability, delay) will be critical to microarchitectural operations in future processors. Thus, we need modeling tools to enable the exploration of such physical interactions and drive development of microarchitectural solutions. This paper introduces a novel framework, Energy Introspector (EI), for the coordinated simulation of microarchitecture and physics models. The EI framework features flexible modeling of processor component hierarchy that enables simulating different microarchitecture and package designs. The proposed framework uses standardized interface to drive different implementations of physics models and captures their interactions. The EI supports parallel computation of models in anticipation of large-scale simulations (e.g., high core-count processors). We present a case study using the EI framework to assess reliability and performance tradeoffs with a full-system cycle-level simulation of an asymmetric chip multiprocessor (ACMP). | en_US |
| dc.embargo.terms | null | en_US |
| dc.identifier.uri | http://hdl.handle.net/1853/53624 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.relation.ispartofseries | CERCS ; GIT-CERCS-09-05 | en_US |
| dc.subject | Asymmetric chip multiprocessor | en_US |
| dc.subject | Energy introspector | en_US |
| dc.subject | Microarchitectural operations | en_US |
| dc.subject | Parallel execution | en_US |
| dc.subject | Performance | en_US |
| dc.subject | Reliability | en_US |
| dc.title | Energy Introspector: Coordinated Architecture-Level Simulation of Processor Physics | en_US |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.author | Mukhopadhyay, Saibal | |
| local.contributor.corporatename | Center for Experimental Research in Computer Systems | |
| local.relation.ispartofseries | CERCS Technical Report Series | |
| relation.isAuthorOfPublication | 62df0580-589a-4599-98af-88783123945a | |
| relation.isOrgUnitOfPublication | 1dd858c0-be27-47fd-873d-208407cf0794 | |
| relation.isSeriesOfPublication | bc21f6b3-4b86-4b92-8b66-d65d59e12c54 |