Title:
Double-Layer No-Flow Underfill Process for Flip-Chip Applications
Double-Layer No-Flow Underfill Process for Flip-Chip Applications
Author(s)
Zhang, Zhuqing
Lu, Jicun
Wong, C. P.
Lu, Jicun
Wong, C. P.
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Abstract
No-flow underfill technology shows potential advances over the conventional underfill technology toward a low-cost flop-chip underfill process. However, due to the filler entrapment in between solder bumps and contact pads on board, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly and has limited its application to large chip assemblies. This paper presents a double-layer no-flow underfill process approach to incorporate silica filler into a no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is filled with silica fillers. The total filler loading of the mixture is estimated to be around 55 wt%. The material properties of each layer of underfills, the underfill mixture, and a control unfilled underfill are characterized using differential scanning calorimeter (DCS), thermo-mechanical analyzer (TMA), dynamic mechanical analyzer (DMA), and a stress rheometer. FB250 daisy-chained test chips are assembled on FR-4 boards using the novel approach. A 100% assembly yield of solder Interconnect is achieved with the double-layer no-flow underfill while in the single-layer no-flow underfill process, no solder joint yield is observed. Scanning electronic microscope (SEM) and optical microscope are used to investigate the cross-section of both assemblies. A US provisional patent has been filed for this invention.
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Date Issued
2003-03
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Article