Title:
Circuit and algorithm design to enable edge intelligence
Circuit and algorithm design to enable edge intelligence
| dc.contributor.advisor | Raychowdhury, Arijit | |
| dc.contributor.author | Cao, Ningyuan | |
| dc.contributor.committeeMember | Lim, Sung-kyu | |
| dc.contributor.committeeMember | Swaminathan, Madhavan | |
| dc.contributor.committeeMember | Bakir, Muhannad S. | |
| dc.contributor.committeeMember | Sen, Shreyas | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2020-09-08T12:47:32Z | |
| dc.date.available | 2020-09-08T12:47:32Z | |
| dc.date.created | 2020-08 | |
| dc.date.issued | 2020-07-22 | |
| dc.date.submitted | August 2020 | |
| dc.date.updated | 2020-09-08T12:47:32Z | |
| dc.description.abstract | “Edge Intelligence” (EI) is a promising alternative to a centralized could-IoT paradigm that has inherent advantages with communication cost, processing latency, data security, network robustness, and so on. However, EI Design is essentially challenging to support ever-demanding artificial intelligence on resource-constrained devices with a slowly-evolving technology node. Moreover, as an emerging field, a systematic investigation is required to facilitate future EI research. This work tends to provide such a comprehensive study on circuit and algorithm solutions for edge intelligence. First, a state-of-art EI overview will be presented along with the proposed EI design landscape, EI evaluation figure-of-merit, and generic EI design methodology. Then, the proposed EI scheme will be elaborated on three sub-topics: EI computation, EI system integration, and distributed EI. Within each sub-topic, a detailed EI platform will be discussed as an example work to illustrate EI design considerations, solutions space, and application scenarios. Finally, conclusions will be drawn to address current and future EI research challenges/opportunities. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/63653 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Edge intelligence | |
| dc.subject | Edge computation | |
| dc.subject | Internet-of-things | |
| dc.subject | System-on-chip | |
| dc.subject | ASIC | |
| dc.subject | Low-power circuit | |
| dc.subject | Machine learning | |
| dc.subject | Artificial intelligence | |
| dc.subject | Micro-robotics | |
| dc.title | Circuit and algorithm design to enable edge intelligence | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Raychowdhury, Arijit | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | c44dbd39-c229-4ffb-9bc0-007eb0904114 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |