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Tummala, Rao R.

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    Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate
    (Georgia Institute of Technology, 2010-11) Wang, Fengtao ; Liu, Fuhan ; Kong, Linghua ; Sundaram, Venky ; Tummala, Rao R. ; Adibi, Ali
    Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher input/outputs (I/O) counts, pushing packaging towards higher density architectures. In the next two to three years, the I/O pitch will fall within 100 μm for area array die and 30 μm for periphery die. That raises an important question to the packaging industry: How will the rapid shrinkage of the I/O pitch affect the package substrate for chip attaching? The answer is sub-10 micron copper line technology. Theoretical and experimental studies on the limitations of using mercury i-line ultraviolet photolithography have been carried at the Packaging Research Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated for flip chip attaching by using semi-additive metallization process.
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    Single sensor that outputs narrowband multispectral images
    (Georgia Institute of Technology, 2010-01) Kong, Linghua ; Yi, Dingrong ; Sprigle, Stephen ; Wang, Fengtao ; Wang, Chao ; Liu, Fuhan ; Adibi, Ali ; Tummala, Rao R.
    We report the work of developing a hand-held (or miniaturized), low-cost, stand-alone, real-time-operation, narrow bandwidth multispectral imaging device for the detection of early stage pressure ulcers.
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    Next-generation microvia and global wiring technologies for SOP
    (Georgia Institute of Technology, 2004-05) Sundaram, Venky ; Tummala, Rao R. ; Liu, Fuhan ; Kohl, Paul A. ; Li, Jun ; Bidstrup-Allen, Sue Ann ; Fukuoka, Yoshitaka
    As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-µm area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 µm diameter and lines and spaces of 25 µm. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for microvia wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 µm and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.