Person:

Tummala, Rao R.

Permanent Link

https://hdl.handle.net/1853/71792

Associated Organization(s)

Organizational Unit

School of Electrical and Computer Engineering

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Publication Search Results

Now showing 1 - 9 of 9

Biomedical implant packaging

(Georgia Institute of Technology, 2011-05-31) Tummala, Rao R. ; Sundaram, Venkatesh
Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate

(Georgia Institute of Technology, 2010-11) Wang, Fengtao ; Liu, Fuhan ; Kong, Linghua ; Sundaram, Venky ; Tummala, Rao R. ; Adibi, Ali

Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher input/outputs (I/O) counts, pushing packaging towards higher density architectures. In the next two to three years, the I/O pitch will fall within 100 μm for area array die and 30 μm for periphery die. That raises an important question to the packaging industry: How will the rapid shrinkage of the I/O pitch affect the package substrate for chip attaching? The answer is sub-10 micron copper line technology. Theoretical and experimental studies on the limitations of using mercury i-line ultraviolet photolithography have been carried at the Packaging Research Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated for flip chip attaching by using semi-additive metallization process.
Single sensor that outputs narrowband multispectral images

(Georgia Institute of Technology, 2010-01) Kong, Linghua ; Yi, Dingrong ; Sprigle, Stephen ; Wang, Fengtao ; Wang, Chao ; Liu, Fuhan ; Adibi, Ali ; Tummala, Rao R.

We report the work of developing a hand-held (or miniaturized), low-cost, stand-alone, real-time-operation, narrow bandwidth multispectral imaging device for the detection of early stage pressure ulcers.
Single sensor that outputs narrowband multispectral images

(Georgia Institute of Technology, 2010-01) Kong, Linghua ; Yi, Dingrong ; Sprigle, Stephen ; Wang, Fengtao ; Wang, Chao ; Liu, Fuhan ; Adibi, Ali ; Tummala, Rao R.

We report the work of developing a hand-held (or miniaturized), low-cost, stand-alone, real-time-operation, narrow bandwidth multispectral imaging device for the detection of early stage pressure ulcers.
Detecting Early Stage Pressure Ulcer on Dark Skin Using Multispectral Imager

(Georgia Institute of Technology, 2010) Yi, Dingrong ; Kong, Linghua ; Sprigle, Stephen ; Wang, Fengtao ; Wang, Chao ; Liu, Fuhan ; Adibi, Ali ; Tummala, Rao R.
Toward high output-power nanogenerator

(Georgia Institute of Technology, 2008-04-29) Liu, Jin ; Fei, Peng ; Zhou, Jun ; Tummala, Rao R. ; Wang, Z. L. (Zhong Lin)

In this paper, the factors that determine the power output of a piezoelectric nanowire (NW) nanogenerator (NG) have been analyzed. The output current is the sum of those contributed by all of the NWs while the output voltage is determined by the voltage generated by a single NW, the capacitance of the NW array and the system, and the contact resistance. By growing uniform ZnO NWs with diameters of ~100 nm and lengths of ~5 µm, the output current density and output voltage of the NG was improved to ~8.3 µA/cm² and 10 mV, respectively, which are 20–30 times higher than that we previously reported. A power generation density of ~83 nW/cm² is achieved by using a single layer NW NG.
Next-generation microvia and global wiring technologies for SOP

(Georgia Institute of Technology, 2004-05) Sundaram, Venky ; Tummala, Rao R. ; Liu, Fuhan ; Kohl, Paul A. ; Li, Jun ; Bidstrup-Allen, Sue Ann ; Fukuoka, Yoshitaka

As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-µm area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 µm diameter and lines and spaces of 25 µm. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for microvia wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 µm and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.
Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package

(Georgia Institute of Technology, 2004-05) Wong, C. P. ; Kang, E. T. ; Tay, Andrew A. O. ; Wong, E. H. ; Swaminathan, Madhavan ; Iyer, Mahadevan K. ; Rotaru, Mihai D. ; Tummala, Rao R. ; Doraiswami, Ravi ; Ang, Simon S. ; Kripesh, V.

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-μm pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.
Development of High Performance Interfill Materials for System Chips Technology

(Georgia Institute of Technology, 2002-06) Wong, C. P. ; Wu, Jiali ; Bhattacharya, Swapan ; Lloyd, Courtney ; Pogge, H. Bernhard ; Tummala, Rao R.

An innovative precisely interconnected chip (PIC) technology is currently under development at IBM to seek more effective means of creating system chips. The objective of this research is developing fabrication methods to permit the realization of high yielding large area chips, as well as chips that may contain very diverse technologies. This paper reports the use of a high-performance interfill material based on epoxy resin, which is used to connect the different chip sector macros that make up the system chip. This novel interfill material remains thermally stable through the subsequent processing temperature hierarchies during the interchip interconnection fabrication. Spherical SiO2 powders are incorporated into the epoxy resin to improve its mechanical properties, reduce coefficient of thermal expansion, and increase thermal conductivity. Adhesion and rheology of the formulated interfill materials are evaluated. Microstructure of SiO2 filled epoxy system is also investigated to confirm the reliability of the composite before and after thermal aging. Initial results indicate that the formulated EPOXY A resin composite is qualified for the system chip manufacturing process in terms of the dispensing processability, structural and mechanical integrity, and reliability.