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Owen, Henry L., III
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Owen
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Henry L., III
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https://hdl.handle.net/1853/71569
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School of Electrical and Computer Engineering
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Owen, Henry L., III
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Schlag, Jay H.
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1989
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MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array
1989-08
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Owen, Henry L., III
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