Title:
MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array
MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array
Author(s)
Owen, Henry L., III
Advisor(s)
Schlag, Jay H.
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Date Issued
1989-08
Extent
237 bytes
Resource Type
Text
Resource Subtype
Dissertation
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Access restricted to authorized Georgia Tech users only.