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Schwan, Karsten

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Author: West, Richard × Author: Yalamanchili, Sudhakar ×

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    Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
    (Georgia Institute of Technology, 2003) Krishnamurthy, Rajaram B. ; Yalamanchili, Sudhakar ; Schwan, Karsten ; West, Richard
    ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design choices and tradeoffs made in the development of a Endsystem/Host-based router realization of the ShareStreams architecture. We evaluate the impact of block decisions and aggregation on the ShareStreams architecture. Using processor resources for queuing and data movement, and FPGA hardware for accelerating stream selection and stream priority updates, ShareStreams can easily meet the wire-speeds of 10Gbps links. This allows provision of customized scheduling solutions and interoperability of scheduling disciplines. FPGA hardware uses a single-cycle Decision block to compare multiple stream attributes simultaneously for pairwise ordering and a Decision block arrangement in a recirculating network to conserve area and improve scalability. Our hardware implemented in the Xilinx Virtex family easily scales from 4 to 32 stream-slots on a single chip. A running FPGA prototype in a PCI card under systems software control can provide scheduling support for a mix of EDF, static-priority and fair-share streams based on user specifications and meet the temporal bounds and packet-time requirements of multi-gigabit links.
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    RASA (Reconfigurable Architectures for Scheduling Activities) Architecture and Hardware for Scheduling Gigabit Packet Streams
    (Georgia Institute of Technology, 2002) Krishnamurthy, Rajaram B. ; Yalamanchili, Sudhakar ; Schwan, Karsten ; West, Richard
    We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and server cluster switches. Our architectural framework can provide EDF, static-priority, fair-share and DWCS native scheduling support for best-effort and real-time streams. This allows (i) interoperability of scheduling hardware supporting different scheduling disciplines and (ii) helps in providing customized scheduling solutions in server clusters based on traffic type, stream content, stream volume and cluster hardware using a hardware implementation of a scheduler running at wire-speeds. The architecture scales easily from 4 to 32 streams on a single Xilinx Virtex 1000 chip and can support 64-byte - 1500-byte Ethernet frames on a 1 Gbps link and 1500-byte Ethernet frames on a 10 Gbps link. A running hardware prototype of a stream scheduler in a Virtex 1000 PCI card can divide bandwidth based on user specifications and meet the temporal bounds and packet-time requirements of multi-gigabit links.
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    QUIC: A Quality of Service Network Interface Layer for Communication in NOWs
    (Georgia Institute of Technology, 2000) West, Richard ; Krishnamurthy, Rajaram B. ; Norton, W. K. (William K.) ; Schwan, Karsten ; Yalamanchili, Sudhakar
    This paper presents the overall project goals from the QUIC project - a joint effort between ECE and CS at Tech. The design of hardware, software Network Interface layers and applications is discussed.