Title:
RASA (Reconfigurable Architectures for Scheduling Activities) Architecture and Hardware for Scheduling Gigabit Packet Streams
RASA (Reconfigurable Architectures for Scheduling Activities) Architecture and Hardware for Scheduling Gigabit Packet Streams
Author(s)
Krishnamurthy, Rajaram B.
Yalamanchili, Sudhakar
Schwan, Karsten
West, Richard
Yalamanchili, Sudhakar
Schwan, Karsten
West, Richard
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Abstract
We present an architecture and hardware for scheduling gigabit packet
streams in server clusters that combines a Network Processor datapath and an FPGA
for use in server NICs and server cluster switches. Our architectural
framework can provide EDF, static-priority, fair-share and DWCS native
scheduling support for best-effort and real-time streams. This allows (i)
interoperability of scheduling hardware supporting different scheduling
disciplines and (ii) helps in providing customized scheduling solutions in
server clusters based on traffic type, stream content, stream volume and
cluster hardware using a hardware implementation of a scheduler running at
wire-speeds. The architecture scales easily from 4 to 32 streams on a single
Xilinx Virtex 1000 chip and can support 64-byte - 1500-byte Ethernet frames
on a 1 Gbps link and 1500-byte Ethernet frames on a 10 Gbps link. A running
hardware prototype of a stream scheduler in a Virtex 1000 PCI card can
divide bandwidth based on user specifications and meet the temporal bounds
and packet-time requirements of multi-gigabit links.
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Date Issued
2002
Extent
379728 bytes
Resource Type
Text
Resource Subtype
Technical Report