Person:
Swaminathan, Madhavan

Associated Organization(s)
ORCID
ArchiveSpace Name Record

Publication Search Results

Now showing 1 - 2 of 2
  • Item
    System Scaling Through Heterogeneous Integration
    (Georgia Institute of Technology, 2019-08-27) Swaminathan, Madhavan
    A combination of "Moore" (IC) and "More than Moore" (package) scaling has led to the shrinking of electronic systems over the last several decades. As scaling continues beyond CMOS to include advanced devices, scaling of the package needs to continue to enable system scaling, leading to the integration and miniaturization of systems. This requires new technologies for package integration which when connected to assembled ICs leads to System on Package (SoP) solutions that have superior performance and size as compared to current technologies. This presentation will discuss advanced SoP platforms for integration with a focus on heterogeneity for a variety of applications that include AI, HPC, Power Electronics, mmWave to name a few. The inter-disciplinary nature of the research will be highlighted based on faculty interactions between four different schools at GT.
  • Item
    Development of compliant free-standing structures for sub 32-nm multi-core ICs
    (Georgia Institute of Technology, 2012-11) Sitaraman, Suresh K. ; Swaminathan, Madhavan
    With the introduction of on-chip low-K dielectric materials, it is increasingly important to reduce on-chip stresses so that the low-K dielectric material will not crack or delaminate. One way to reduce the thermo-mechanical stresses is to introduce compliant structures between the die and the substrate and thus to decouple the die from the substrate. Decoupling the die from the substrate or the substrate from the board by means of mechanically compliant interconnects will reduce stresses created by the coefficient of thermal expansion mismatch. A decoupled diesubstrate or substrate-board interface will allow the different components to expand or contract differently without inducing high stresses in the components. In this work, we report the design, fabrication, modeling, and characterization of innovative multi-path fan-shaped off-chip compliant interconnects. The proposed interconnects can be fabricated at the wafer-level and are cost-effective, can be of fine pitch and scalable, and will have redundant electrical paths.