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Wong,
C. P.
Wong,
C. P.
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ItemNovel Reworkable Fluxing Underfill for Board-Level Assembly(Georgia Institute of Technology, 2004-09) Wong, C. P. ; Zhang, Zhuqing ; Li, HaiyingUnderfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.
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ItemRecent Advances in Flip-Chip Underfill: Materials, Process, and Reliability(Georgia Institute of Technology, 2004-08) Wong, C. P. ; Zhang, ZhuqingIn order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.
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ItemModeling of the Curing Kinetics of No-Flow Underfill in Flip-Chip Applications(Georgia Institute of Technology, 2004-06) Wong, C. P. ; Zhang, ZhuqingNo-flow underfill has greatly improved the production efficiency of flip-chip process. Due to its unique characteristics, including reaction latency, curing under solder reflow conditions and the desire for no post-cure, there is a need for a fundamental understanding of the curing process of no-flow underfill. Starting with a promising no-flow underfill formulation, this paper seeks to develop a systematic methodology to study and model the curing behavior of this underfill. A differential scanning calorimeter (DSC) is used to characterize the heat flow during curing under isothermal and temperature ramp conditions. A modified autocatalytic model is developed with temperature-dependent parameters. The degree of cure (DOC) is calculated; compared with DSC experiments, the model gives a good prediction of DOC under different curing conditions. The temperature of the printed wiring board (PWB) during solder reflow is measured using thermocouples and the evolution of DOC of the no-flow underfill during the reflow process is calculated. A stress rheometer is used to study the gelation of the underfill at different heating rates. Results show that at high curing temperature, the underfill gels at a lower DOC. Based on the kinetic model and the gelation study, the solder wetting behavior during the eutectic SnPb and lead-free SnAgCu reflow processes is predicted and confirmed by the solder wetting tests.
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ItemFEM Modeling of Temperature Distribution of a Flip-Chip No-Flow Underfill Package During Solder Reflow Process(Georgia Institute of Technology, 2004-01) Wong, C. P. ; Zhang, Zhuqing ; Sitaraman, Suresh K.Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.