Person:
Naeemi,
Azad
Publication Search Results
Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication
Person:
Naeemi,
Azad
1 - 1 of 1
Item
Polylithic integration of electrical and optical interconnect
technologies is presented as a solution for merging silicon
CMOS and compound semiconductor optoelectronics. In contrast
to monolithic and hybrid integration technologies, polylithic integration
allows for the elimination of optoelectronic and integrated
optic device-related processing from silicon CMOS manufacturing.
Printed wiring board-level and compound semiconductor
chip-level waveguides terminated with volume grating couplers facilitate
bidirectional optical communication, where fiber-to-board
and board-to-chip optical coupling occurs through a two-grating
(or grating-to-grating) coupling path. A 27% increase in the electrical
signal I/O projected by and 33% increase in the number of
substrate-level electrical signal interconnect layers implied by the
International Technology Roadmap for Semiconductors (ITRS)
projections for the 32-nm technology generation are required to
facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication.
Buried air-gap channels provide for the routing of chip
or board-level encapsulated air-clad waveguides for minimum
crosstalk and maximum interconnect density. Optical signals
routed on-board communicate with on-chip volume grating couplers
embedded as part of a wafer-level batch package technology
exhibiting compatible electrical and optical input/output interconnects.
Measurements of grating-to-grating coupling reveal 31%
coupling efficiency between two slab, nonoptimized, nonfocusing
volume grating couplers.