Naeemi, Azad

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Now showing 1 - 5 of 5
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    Performance Modeling, Design, and Benchmarking for Beyond-CMOS Devices and Circuits
    (Georgia Institute of Technology, 2017-11-28) Naeemi, Azad
    A diverse set of novel materials, physical phenomena, interconnects, logic and memory devices, and circuit/system concepts are being studied globally to sustain the exponential growth of the computational power of integrated circuits. As such, the search for beyond-CMOS devices and circuits must deal with all the levels of abstraction and must take a holistic approach to evaluate the potential performance of each possible option. In this talk, I will first present physical models for electronic and spintronic transport properties of various conventional and emerging materials such as graphene, Si and Cu. Then I will present compact physical models (SPICE models) for various physical phenomena such as nanomagnet dynamics, spin-orbit coupling and spin waves. The utilization of these models for device modeling will then be discussed and I will show how these models can be used to model the behavior of some of the proposed beyond-CMOS devices and to evaluate their potential performance once they are used in various representative Boolean and neuromorphic circuits. Through several examples, I will show how this process can be used to identify the main limiting factors for each device and to revise and refine them.
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    Carbon-Based Interconnects for Nanoelectronic Systems
    (Georgia Institute of Technology, 2009-04-07) Naeemi, Azad
    Interconnects have long been considered a major limitation for integrated circuits because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. These problems are all exacerbated as interconnect dimensions scale to the dimensions comparable or even smaller than the mean free path of electrons in bulk copper. Carbon nanotubes and graphene nanoribbons are being investigated as potential solutions to the challenges facing nanoscale interconnects because of their extremely large capacity for electrical and thermal conduction. Most of the fascinating properties of carbon nanomaterials can be attributed to their one dimensional nature, the exceptionally strong carbon bonds, and the peculiar bandstructure of graphene. In this talk, physical models are presented for carbon nanotube and graphene nanoribbon interconnects. These models are then used to benchmark them against conventional copper interconnects. The results offer important guidelines for technology development of these novel interconnects.
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    Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication
    (Georgia Institute of Technology, 2005-08) Mule’, Anthony V. ; Villalaz, Ricardo A. ; Joseph, Paul Jayachandran ; Naeemi, Azad ; Kohl, Paul A. ; Gaylord, Thomas K. ; Meindl, James D.
    Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.
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    Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization
    (Georgia Institute of Technology, 2004-04) Naeemi, Azad ; Xu, Jianping ; Mule’, Anthony V. ; Gaylord, Thomas K. ; Meindl, James D.
    The lengths beyond which board-level optical waveguides are capable of transferring a larger number of bits per second than electrical interconnects are found for various technology generations. As technology scales from the 130-nm technology node to the 45-nm technology node, the partition length falls from 29 to 8.3 cm due to seven times larger driver-switching frequency and 40% finer waveguide pitches.
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    Analysis and optimization for global interconnects for gigascale integration (GSI)
    (Georgia Institute of Technology, 2003-12-01) Naeemi, Azad