(Georgia Institute of Technology, 2005-08)
Mule’, Anthony V.; Villalaz, Ricardo A.; Joseph, Paul Jayachandran; Naeemi, Azad; Kohl, Paul A.; Gaylord, Thomas K.; Meindl, James D.
Polylithic integration of electrical and optical interconnect
technologies is presented as a solution for merging silicon
CMOS and compound semiconductor optoelectronics. In contrast
to monolithic and hybrid integration technologies, polylithic integration
allows for the elimination of optoelectronic and integrated
optic device-related processing from silicon CMOS manufacturing.
Printed wiring board-level and compound semiconductor
chip-level waveguides terminated with volume grating couplers facilitate
bidirectional optical communication, where fiber-to-board
and board-to-chip optical coupling occurs through a two-grating
(or grating-to-grating) coupling path. A 27% increase in the electrical
signal I/O projected by and 33% increase in the number of
substrate-level electrical signal interconnect layers implied by the
International Technology Roadmap for Semiconductors (ITRS)
projections for the 32-nm technology generation are required to
facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication.
Buried air-gap channels provide for the routing of chip
or board-level encapsulated air-clad waveguides for minimum
crosstalk and maximum interconnect density. Optical signals
routed on-board communicate with on-chip volume grating couplers
embedded as part of a wafer-level batch package technology
exhibiting compatible electrical and optical input/output interconnects.
Measurements of grating-to-grating coupling reveal 31%
coupling efficiency between two slab, nonoptimized, nonfocusing
volume grating couplers.
(Georgia Institute of Technology, 2004-04)
Naeemi, Azad; Xu, Jianping; Mule’, Anthony V.; Gaylord, Thomas K.; Meindl, James D.
The lengths beyond which board-level optical waveguides
are capable of transferring a larger number of bits per second
than electrical interconnects are found for various technology generations.
As technology scales from the 130-nm technology node
to the 45-nm technology node, the partition length falls from 29 to
8.3 cm due to seven times larger driver-switching frequency and
40% finer waveguide pitches.