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Lim, Sung Kyu

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Author: Balakrishnan, Karthik × End date: 2007 × Start date: 2003 ×

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Wire Congestion And Thermal Aware Global Placement For 3D VLSI Circuits

2004-05-26 , Balakrishnan, Karthik , Nanda, Vidit , Easwar, Siddharth Sangam , Lim, Sung Kyu

The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce global the temperature gradient and local and global congestions of 3D circuit designs without compromising total intra-layer wirelength or inter-layer via count. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local wire congestion and power dissipation. Then, we perform simulated annealing with a full-length thermal analysis to reduce the circuit's global congestion and thermal gradient. Experimental results show that when compared to the standard mincut approach, our thermal gradient and local congestion are reduced by 25% each, global congestion is reduced by over 7%. Moreover, we only see a 10% increase in the wiring length and the number of vias required.

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Impact of Multi-level Clustering on Performance Driven Global Placement

2003 , Balakrishnan, Karthik , Nanda, Vidit , Ekpanyapong, Mongkol , Lim, Sung Kyu

Delay and wirelength minimization continue to be important objectives in the design of high-performance computing systems. For large-scale circuits, the clustering process becomes essential for reducing the problem size. However, to the best of our knowledge, there is no study about the impact of multi-level clustering on performance-driven global placement. In this paper, five clustering algorithms including the quasi-optimal retiming delay driven PRIME and the cutsize-driven ESC have been considered for their impact on state-of-the-art mincut based global placement. Results show that minimizing cutsize or wirelength during clustering typically results in significant performance improvements.

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Congestion-Driven Global Placement for Three Dimensional VLSI Circuits

2003 , Nanda, Vidit , Balakrishnan, Karthik , Ekpanyapong, Mongkol , Lim, Sung Kyu

The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, the problem of thermal dissipation is magnified due to the nature of these layered technologies. In this paper, we develop techniques to reduce both the local and global congestions of 3D circuit designs in order to alleviate thermal issues. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local congestion. Then, we perform simulated annealing to reduce the circuit's global congestion. Experimental results show that our local congestion is reduced by an average of over 44% and global congestion is reduced by over 16%. Moreover, we only see an 11% increase in the wiring length and the number of vias required.

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