(Georgia Institute of Technology, 2004)
Pfeiffenberger, Philipp; Park, Jun Cheol; Mooney, Vincent John, III
This technical report elaborates on the methodology and findings presented in “Sleepy Stack Reduction of Leakage Power” by J.C. Park, V. J. Mooney III and P. Pfeiffenberger [1]. The scope of this report includes test procedures and data on delay, dynamic and static power for all considered approaches and implementations as well as schematics and layouts for all considered approaches and implementations.
(Georgia Institute of Technology, 2003)
Balasundaram, Arunkumar; Pereira, Angelo W. D.; Park, Jun Cheol; Mooney, Vincent John, III
This technical report describes AGNI (meaning Fire in Sanskrit) – a VLSI chip to implement
error control codes. The chip was initially conceived and designed as part of a Georgia Tech
Cutting Edge Research Grant. However, this chip implementation of error control codes has
been undertaken as a part of the ECE 6130 course taught in Spring 2002 by Dr. John
Uyemura, Professor, Department of Electrical and Computer Engineering, Georgia Institute
of Technology. Two coders have been implemented: a (12, 6, 4) wavelet encoder/decoder
and a (24, 12, 8) golay encoder/decoder, where the (N, M, d) nomenclature stands for
(N=encoded length, M=message length, d=hamming distance). These codes have a
correctable limit of one bit error and three bit errors, respectively. The following section
presents the encoding/decoding functionality of the chip in more detail.
This project could potentially feed a future project to incorporate the chip into a System-ona-
Package (SoP). It is expected that the chip would function as a high-speed error
encoder/decoder for Radio Frequency (RF) applications.