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Chatterjee, Abhijit

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Signal acquisition of high-speed periodic signals using incoherent sub-sampling and back-end signal reconstruction algorithms

2009-02 , Chatterjee, Abhijit , Gomes, Alfred V. , Choi, Hyun

This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and backend signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and suppression of jitter-induced sampling noise. By switching the sampling rate of a digitizer, the analog frequency value of the sampled signal can be recovered. The proposed signal reconstruction uses incoherent sub-sampling to reduce hardware complexity. The results of simulation and hardware experiments indicate that the proposed signal reconstruction algorithms are able to reconstruct multi-tone high-speed periodic signals in the discrete time domain. The new signal acquisition technique simplifies signal acquisition hardware for testing and characterization of high-speed analog and digital signals.

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Low-cost testing of ADCs and DACs

2006-12-01 , Chatterjee, Abhijit , Goyal, Shalabh

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Hierarchical Power Optimization for System-on-a-Chip (SoC)through CMOS Technology Scaling

2002 , Choi, Kyu-Won , Chatterjee, Abhijit

This report describes an efficient hierarchical design and optimization approach for ultra-low power and minimum area CMOS logic circuits in a system-on-a-chip (SoC) design environment. For state of the art systems, the trade-off solutions between the conflicting design criteria (Delay, Area, and Power) should be considered. In this report, we consider interactions between abstraction levels of the design hierarchy and present techniques that co-optimize the power and the area without performance degradation through judiciously explored technology parameters: Supply voltage, Threshold voltage, and Device width. Experimental results deliver over an order of magnitude savings in power over conventional optimization methods.

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