Title:
Hierarchical Power Optimization for System-on-a-Chip (SoC)through CMOS Technology Scaling
Hierarchical Power Optimization for System-on-a-Chip (SoC)through CMOS Technology Scaling
Author(s)
Choi, Kyu-Won
Chatterjee, Abhijit
Chatterjee, Abhijit
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Abstract
This report describes an efficient hierarchical design and optimization
approach for ultra-low power and minimum area CMOS logic circuits in a
system-on-a-chip (SoC) design environment. For state of the art systems, the
trade-off solutions between the conflicting design criteria (Delay, Area,
and Power) should be considered. In this report, we consider interactions
between abstraction levels of the design hierarchy and present techniques
that co-optimize the power and the area without performance degradation
through judiciously explored technology parameters: Supply voltage,
Threshold voltage, and Device width. Experimental results deliver over an
order of magnitude savings in power over conventional optimization methods.
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Date Issued
2002
Extent
392826 bytes
Resource Type
Text
Resource Subtype
Technical Report