Organizational Unit:
Center for Experimental Research in Computer Systems
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ILP-based Supply and Threshold Voltage Assignment For Total Power Minimization
Channel and Pin Assignment for Three Dimensional Packaging Routing
Impact of Multi-level Clustering on Performance Driven Global Placement
Thermal-driven Circuit Partitioning and Floorplanning with Power Optimization
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors
Congestion and Power Integrity Aware Placement and Routing for 3D Packaging
Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
Wire Congestion And Thermal Aware Global Placement For 3D VLSI Circuits
Thermal-aware 3D Microarchitectural Floorplanning
Congestion-Driven Global Placement for Three Dimensional VLSI Circuits