Series
CERCS Technical Report Series

Permanent Link
https://hdl.handle.net/1853/70997
Series Type
Publication Series
Description
Associated Organization(s)
Associated Organization(s)

Filters

2003 - 2004 3
3
3
3
Reset filters

Settings
Author: Ekpanyapong, Mongkol × Author: Lee, Hsien-Hsin Sean × Type: Text ×

Publication Search Results

Now showing 1 - 3 of 3
  • Thumbnail Image
    Item
    Thermal-aware 3D Microarchitectural Floorplanning
    (Georgia Institute of Technology, 2004) Ekpanyapong, Mongkol ; Healy, Michael ; Ballapuram, Chinnakrishnan S. ; Lim, Sung Kyu ; Lee, Hsien-Hsin Sean ; Loh, Gabriel H.
    Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper pipelines and higher clock frequency. The move to 3D ICs will also likely be used to further shorten wirelength. This will cause thermal issues to become a major bottleneck to performance improvement. In this paper we propose a floorplanning algorithm which takes into consideration both thermal issues and profile weighted wirelength using mathematical programming. Our profile-driven objective improves performance by 20% over wirelength-driven. While the thermal-driven objective improves temperature by 24% on average over the profile-driven case.
  • Thumbnail Image
    Item
    Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
    (Georgia Institute of Technology, 2003) Ekpanyapong, Mongkol ; Minz, Jacob Rajkumar ; Watewai, Thaisiri ; Lee, Hsien-Hsin Sean ; Lim, Sung Kyu
    As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying the performance scalability substantially. An effective floorplanning algorithm can no longer ignore the information of dynamic communication patterns of applications. In this paper, using the profile information acquired at the architecture/microarchitecture level, we propose a "profile-guided microarchitectural floorplanner" that considers both the impact of wire delay and the architectural behavior, namely the inter-module communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on our simulation results, the profile-guided method shows a 5% to 40% IPC improvement when clock frequency is fixed. From the perspective of instruction throughput (in BIPS), our floorplanner is much more scalable than a conventional wire length based floorplanner.
  • Thumbnail Image
    Item
    Choice Predictor for Free
    (Georgia Institute of Technology, 2003) Ekpanyapong, Mongkol ; Korkmaz, Pinar ; Lee, Hsien-Hsin Sean
    Reducing energy consumption has become the first priority in designing microprocessors for all market segments including embedded, mobile, and high performance processors. The trend of state-of-the-art branch predictor designs such as a hybrid predictor continues to feature more and larger prediction tables, thereby exacerbating the energy consumption. In this paper, we present two novel profile-guided static prediction techniques--- Static Correlation Choice (SCC) prediction and Static Choice (SC) prediction for alleviating the energy consumption without compromising performance. Using our techniques, the hardware choice predictor of a hybrid predictor can be completely eliminated from the processor and replaced with our off-line profiling schemes. Our simulation results show an average 40% power reduction compared to several hybrid predictors. In addition, an average 27% die area can be saved in the branch predictor hardware for other performance features.