Title:
Bus Interconnect Structure for a System-on-a-Chip Multiprocessor System
Bus Interconnect Structure for a System-on-a-Chip Multiprocessor System
| dc.contributor.author | Talpasanu, Alexandru | en_US |
| dc.date.accessioned | 2005-06-17T17:35:25Z | |
| dc.date.available | 2005-06-17T17:35:25Z | |
| dc.date.issued | 2004 | en_US |
| dc.description.abstract | This report describes two possible implementations for a bus interconnect structure which would be used in a multiprocessor System-On-a-Chip. The bus architecture is called the GGBA (General Global Bus Architecture.) The research findings presented in this report show that from two possible implementations for a system bus for this bus architecture, one of those would be the most advantageous based on factors such as bus latency, crosstalk, and bus area. | en_US |
| dc.format.extent | 159411 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/6488 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.relation.ispartofseries | CC Technical Report; GIT-CC-04-03 | en_US |
| dc.subject | System-on-a-Chip (SoC) | |
| dc.subject | Bus architecture | |
| dc.subject | Interconnects | |
| dc.title | Bus Interconnect Structure for a System-on-a-Chip Multiprocessor System | en_US |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | College of Computing | |
| local.relation.ispartofseries | College of Computing Technical Report Series | |
| relation.isOrgUnitOfPublication | c8892b3c-8db6-4b7b-a33a-1b67f7db2021 | |
| relation.isSeriesOfPublication | 35c9e8fc-dd67-4201-b1d5-016381ef65b8 |
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