Title:
A combined top-down/bottom-up route to fabricating graphene devices
A combined top-down/bottom-up route to fabricating graphene devices
| dc.contributor.advisor | Cressler, John D. | |
| dc.contributor.author | Hicks, Jeremy David | |
| dc.contributor.committeeMember | Naeemi, Azad | |
| dc.contributor.committeeMember | Gaylord, Thomas K | |
| dc.contributor.committeeMember | Adibi, Ali | |
| dc.contributor.committeeMember | Conrad, Edward H. | |
| dc.contributor.committeeMember | de Heer, Walt A. | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2013-09-20T13:27:09Z | |
| dc.date.available | 2013-09-20T13:27:09Z | |
| dc.date.created | 2013-08 | |
| dc.date.issued | 2013-06-28 | |
| dc.date.submitted | August 2013 | |
| dc.date.updated | 2013-09-20T13:27:09Z | |
| dc.description.abstract | The purpose of this work is to explore a method that combines both top-down and bottom-up elements to fabricate electronic devices made from graphene, a single sheet of carbon atoms related to carbon nanotubes and graphite. This material has garnered interest in the semiconductor industry for many reasons, including its potential for ballistic conduction, natural ambipolar (both n- and p-type) carrier transport, and impermeability to nearly all elements. However, its lack of a band gap, and a lack of viable options for creating one in the material, suggests a limited future as a silicon replacement material. A solution to this problem is presented that uses a recently-reported technique of creating pre-patterned graphene features from the thermal decomposition of specially-structured silicon carbide (SiC) surfaces. We employ a combination of direct band structure measurements and electrical results to suggest that a semiconducting bent graphene nanostructure exists in this structured SiC system, creating a possible route toward a broad class of future graphene electronics. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/49100 | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Graphene | |
| dc.subject | Silicon carbide | |
| dc.subject | ARPES | |
| dc.subject | Surface science | |
| dc.subject.lcsh | Electronic apparatus and appliances | |
| dc.subject.lcsh | Carbon nanotubes | |
| dc.subject.lcsh | Graphite | |
| dc.subject.lcsh | Semiconductors | |
| dc.title | A combined top-down/bottom-up route to fabricating graphene devices | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Cressler, John D. | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | 2df1dcb5-f1ce-4e65-a1eb-021f8a8ab8bc | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |