Title:
Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication
Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication
| dc.contributor.author | Mule’, Anthony V. | |
| dc.contributor.author | Villalaz, Ricardo A. | |
| dc.contributor.author | Joseph, Paul Jayachandran | |
| dc.contributor.author | Naeemi, Azad | |
| dc.contributor.author | Kohl, Paul A. | |
| dc.contributor.author | Gaylord, Thomas K. | |
| dc.contributor.author | Meindl, James D. | |
| dc.contributor.corporatename | Georgia Institute of Technology. Center for Organic Photonics and Electronics | en_US |
| dc.contributor.corporatename | Georgia Institute of Technology. School of Chemical and Biomolecular Engineering | en_US |
| dc.contributor.corporatename | Georgia Institute of Technology. School of Electrical and Computer Engineering | en_US |
| dc.contributor.corporatename | Georgia Institute of Technology. Microelectronics Research Center | en_US |
| dc.contributor.corporatename | Intel Corporation | en_US |
| dc.date.accessioned | 2013-05-17T20:02:39Z | |
| dc.date.available | 2013-05-17T20:02:39Z | |
| dc.date.issued | 2005-08 | |
| dc.description | © 2005 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en_US |
| dc.description | DOI: 10.1109/TADVP.2005.847838 | |
| dc.description.abstract | Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers. | en_US |
| dc.embargo.terms | null | en_US |
| dc.identifier.citation | Mule’, A.V.; Villalaz, R.A.; Joseph, P.J.; Naeemi, A.; Kohl, P.A.; Gaylord, Thomas K. and Meindl, J.D., "Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication," IEEE Transactions on Advanced Packaging, Vol. 28, no.3, pp.421-433 (August 2005). | en_US |
| dc.identifier.doi | 10.1109/TADVP.2005.847838 | |
| dc.identifier.issn | 1521-3323 (print) | |
| dc.identifier.uri | http://hdl.handle.net/1853/46949 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.publisher.original | Institute of Electrical and Electronics Engineers | |
| dc.subject | High-speed interconnects | en_US |
| dc.subject | Integrated optics | en_US |
| dc.subject | Optical | en_US |
| dc.subject | Optical interconnects | en_US |
| dc.subject | Optoelectronic packaging | en_US |
| dc.subject | System level | en_US |
| dc.title | Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication | en_US |
| dc.type | Text | |
| dc.type.genre | Article | |
| dspace.entity.type | Publication | |
| local.contributor.author | Gaylord, Thomas K. | |
| local.contributor.author | Kohl, Paul A. | |
| local.contributor.author | Naeemi, Azad | |
| local.contributor.corporatename | Center for Organic Photonics and Electronics | |
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