Title:
A design methodology for robust, energy-efficient, application-aware memory systems
A design methodology for robust, energy-efficient, application-aware memory systems
| dc.contributor.advisor | Mukhopadhyay, Saibal | |
| dc.contributor.author | Chatterjee, Subho | |
| dc.contributor.committeeMember | Bakir, Muhannad | |
| dc.contributor.committeeMember | Chatterjee, Abhijit | |
| dc.contributor.committeeMember | Kumar, Satish | |
| dc.contributor.committeeMember | Yalamanchili, Sudhakar | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2014-01-10T19:36:41Z | |
| dc.date.available | 2014-01-10T19:36:41Z | |
| dc.date.issued | 2012-08-28 | |
| dc.description.abstract | Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit and device level innovations are required for existing memory technologies. Emerging memory solutions are widely explored to cater to strict budgets. This thesis presents design methodologies for custom memory design with the objective of power-performance benefits across specific applications. Taking example of STTRAM (spin transfer torque random access memory) as an emerging memory candidate, the design space is explored to find optimal energy design solution. A thorough thermal reliability study is performed to estimate detection reliability challenges and circuit solutions are proposed to ensure reliable operation. Adoption of the application-specific optimal energy solution is shown to yield considerable energy benefits in a read-heavy application called MBC (memory based computing). Circuit level customizations are studied for the volatile SRAM (static random access memory) memory, which will provide improved energy-delay product (EDP) for the same MBC application. Memory design has to be aware of upcoming challenges from not only the application nature but also from the packaging front. Taking 3D die-folding as an example, SRAM performance shift under die-folding is illustrated. Overall the thesis demonstrates how knowledge of the system and packaging can help in achieving power efficient and high performance memory design. | |
| dc.description.degree | Ph.D. | |
| dc.identifier.uri | http://hdl.handle.net/1853/50146 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Application-aware | |
| dc.subject | SRAM | |
| dc.subject | STTRAM | |
| dc.subject.lcsh | Integrated circuits Very large scale integration | |
| dc.subject.lcsh | Memory management (Computer science) | |
| dc.subject.lcsh | Computer storage devices | |
| dc.subject.lcsh | Random access memory | |
| dc.title | A design methodology for robust, energy-efficient, application-aware memory systems | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Mukhopadhyay, Saibal | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | 62df0580-589a-4599-98af-88783123945a | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |
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