Title:
A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays

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dc.contributor.advisor Schimmel, David E.
dc.contributor.author Clark, Christopher R. en_US
dc.contributor.committeeMember Keezer, David C.
dc.contributor.committeeMember Blough, Douglas M.
dc.contributor.committeeMember Lee, Hsien-Hsin Sean
dc.contributor.committeeMember Wenke Lee
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2007-03-27T18:29:31Z
dc.date.available 2007-03-27T18:29:31Z
dc.date.issued 2006-08-28 en_US
dc.description.abstract The objective of this dissertation is to develop a methodology for describing the functionality, analyzing the complexity, and evaluating the performance of a large class of pattern-matching circuit design approaches for field-programmable gate arrays (FPGAs). The developed methodology consists of three elements. The first is a functional model and associated nomenclature that unifies a significant portion of published circuit design approaches while also illuminating many novel approaches. The second is a set of analytical expressions that model the area and time complexity of each circuit design approach based on attributes of a given pattern set. Third, software tools are developed that facilitate architectural design space exploration and circuit implementation. This methodology is used to conduct an extensive evaluation and comparison of design approaches under a wide range of conditions using pattern sets from multiple application domains as well as synthetic pattern sets. The results indicate strong dependences between pattern set properties and circuit performance and provide new insights on the fundamental nature of various design approaches. A number of techniques have been proposed for designing pattern-matching hardware circuits with reconfigurable FPGA chips. The use of FPGAs enables high performance because the circuits can be customized for a particular application and pattern set. A relatively unstudied consequence of tailoring circuits for specific patterns is that circuit area and performance are affected by various properties of the patterns used. Most previous work in this field only considers a single design approach and a small number of pattern sets. Therefore, it is not clear how each design is affected by pattern set properties. For a given set of patterns, it is difficult to determine which approach would be the most efficient or provide the highest performance. Previous attempts to compare approaches using results from different publications are conflicting and inconclusive due to variations in the FPGA devices, patterns, and circuit optimizations used. There has been no attempt to evaluate a wide range of designs under a common set of conditions. The methodology presented in this dissertation provides a framework for studying multiple aspects of FPGA pattern-matching circuits in a controlled and consistent manner. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 1355546 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/14138
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Finite automata en_US
dc.subject Brute force en_US
dc.subject Pattern-matching en_US
dc.subject FPGA en_US
dc.subject NFA en_US
dc.subject DFA en_US
dc.title A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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