Title:
Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching
Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching
Author(s)
Woo, Dong Hyuk
Fryman, Joshua B.
Knies, Allan D.
Lee, Hsien-Hsin Sean
Fryman, Joshua B.
Knies, Allan D.
Lee, Hsien-Hsin Sean
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Abstract
Heterogeneous multi-core processors have emerged as an energy- and area-efficient architectural solution to
improving performance for domain-specific applications such as those with a plethora of data-level parallelism.
These processors typically contain a large number of small, compute-centric cores for acceleration while keeping one
or two high-performance ILP cores on the die to guarantee single-thread performance. Although a major portion of
the transistors are occupied by the acceleration cores, these resources will sit idle when running unparallelized legacy
codes or the sequential parts of an application. To address this under-utilization issue, in this paper, we introduce
Chameleon, a flexible heterogeneous multi-core architecture to virtualize these resources for enhancing memory
performance when running sequential programs. The Chameleon architecture can dynamically virtualize the idle
acceleration cores into a last-level cache, a data prefetcher, or a hybrid between these two techniques. In addition,
Chameleon can operate in an adaptive mode which dynamically configures the acceleration cores between the hybrid
mode and the prefetch-only mode by monitoring the effectiveness of Chameleon caching scheme. In our evaluation
using SPEC2006 benchmark suite, different levels of performance improvements were achieved in different modes
for different applications. In the case of the adaptive mode, Chameleon improves the performance of SPECint06
and SPECfp06 by 33% and 22% on average. When considering only memory-intensive applications, Chameleon
improves the system performance by 53% and 33%.
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Date Issued
2008
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Technical Report