Title:
A Delay-Locked Loop for Multiple Clock Phases/Delays Generation
A Delay-Locked Loop for Multiple Clock Phases/Delays Generation
| dc.contributor.advisor | Milor, Linda S. | |
| dc.contributor.author | Jia, Cheng | en_US |
| dc.contributor.committeeMember | Abhijit Chatterjee | |
| dc.contributor.committeeMember | Alfred D. Anew | |
| dc.contributor.committeeMember | David Keezer | |
| dc.contributor.committeeMember | Cressler, John D. | |
| dc.contributor.committeeMember | Russell Callen | |
| dc.contributor.department | Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2006-01-18T22:13:44Z | |
| dc.date.available | 2006-01-18T22:13:44Z | |
| dc.date.issued | 2005-08-24 | en_US |
| dc.description.abstract | A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using this structure, a fast switching speed can be achieved. Moreover, the combined PD and CP also lead to reduced chip area and better jitter performance. A novel phase detection algorithm is developed and implemented in the combined PD and CP structure. This algorithm also involves a start-control circuit to avoid locking failure or false lock to harmonics. With the help of this algorithm, the proposed DLL is able to achieve lock as long as the minimum VCDL delay is less than one reference clock cycle, which is the largest possible lock range that can be achieved by the DLL. The VCDL uses fully differential signaling to minimize jitter. The delay stage of the VCDL is built with a differential topology using symmetrical loads and replica-feedback biasing, which provides a low sensitivity to supply and substrate noise as well as a wide tuning range. In addition, a shift-averaging technique is used to improve the matching between delay stages and thus to equalize the delay of each individual stage. | en_US |
| dc.description.degree | Ph.D. | en_US |
| dc.format.extent | 1204998 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/7470 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.subject | Delay-locked loop | en_US |
| dc.subject.lcsh | Code division multiple access | en_US |
| dc.subject.lcsh | Integrated circuits Design and construction | en_US |
| dc.subject.lcsh | Phase-locked loops Design and construction | en_US |
| dc.subject.lcsh | Timing circuits Design and construction | en_US |
| dc.title | A Delay-Locked Loop for Multiple Clock Phases/Delays Generation | en_US |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Milor, Linda S. | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | fbe5d5c9-48f4-4624-a928-ba45e51a4f54 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |
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