Title:
Variable Interconnect Geometry For Electronic Packages And Fabrication Methods

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dc.contributor.patentcreator Sitaraman, Suresh K.
dc.contributor.patentcreator Kacker, Karan
dc.contributor.patentcreator Sokol, Thomas
dc.date.accessioned 2017-05-12T14:26:23Z
dc.date.available 2017-05-12T14:26:23Z
dc.date.filed 5/24/2007
dc.date.issued 7/1/2014
dc.description.abstract Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
dc.description.assignee Georgia Tech Research Corporation
dc.identifier.cpc H01L24/11
dc.identifier.cpc H01L24/13
dc.identifier.cpc H01R13/2407
dc.identifier.patentapplicationnumber 11/805693
dc.identifier.patentnumber 8766449
dc.identifier.uri http://hdl.handle.net/1853/56895
dc.identifier.uspc 257/773
dc.title Variable Interconnect Geometry For Electronic Packages And Fabrication Methods
dc.type Text
dc.type.genre Patent
dspace.entity.type Publication
local.contributor.corporatename Georgia Institute of Technology
local.relation.ispartofseries Georgia Tech Patents
relation.isOrgUnitOfPublication cc30e153-7a64-4ae2-9b1d-5436686785e3
relation.isSeriesOfPublication 0f49c79d-4efb-4bd9-b060-5c7f9191b9da
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