Title:
Cache Sensitive Instruction Scheduling

dc.contributor.author Hardnett, Charles R. en_US
dc.contributor.author Rabbah, Rodric Michel
dc.contributor.author Palem, Krishna V.
dc.contributor.author Wong, Weng Fai
dc.date.accessioned 2005-06-17T17:43:25Z
dc.date.available 2005-06-17T17:43:25Z
dc.date.issued 2001 en_US
dc.description.abstract The processor speeds continue to improve at a faster rate than the memory access times. The issue of data locality is still unsolved, and continues to be a problem given the widening gap between processor speeds and memory access times. Compiler research has chosen to address this problem in many directions including source code transformations of loops, static data reorganization, dynamic data reorganization, and optimized instruction scheduling. This paper presents Cache Sensitive Scheduling(CSS). CSS is an instruction scheduling algorithm that relies on a rank function to choose operations in the proper order. The CSS rank function is built on the latency of the operation, the impact of this operation on other operations in the program, and the latency of operations that this operation is dependent on in some way. Our premise is based on the hypothesis that careful scheduling of load instructions can increase ILP and decrease execution times by overlaying the latency of load instructions with other useful instructions. This is particular useful on EPIC and VLIW types of machines, where increased ILP is always a benefit. Our rank function is designed to find these opportunities and exploit them. We will show that these techniques can be used to improve the performance of programs with a range of memory access patterns spanning the regular to irregular. en_US
dc.format.extent 230336 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/6569
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.relation.ispartofseries CC Technical Report; GIT-CC-01-15 en_US
dc.subject Scheduling
dc.subject Cache sensitive scheduling (CSS)
dc.title Cache Sensitive Instruction Scheduling en_US
dc.type Text
dc.type.genre Technical Report
dspace.entity.type Publication
local.contributor.corporatename College of Computing
local.relation.ispartofseries College of Computing Technical Report Series
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
relation.isSeriesOfPublication 35c9e8fc-dd67-4201-b1d5-016381ef65b8
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